From 71b346c3ef20fbb6b9ed7c84681a40876d0c7415 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Tue, 7 May 2019 16:54:16 -0600 Subject: kohaku: Correct SYS_RESET_L pin # in gpio.inc SYS_RESET_L# is routed to GPIOC5 and not GPIO02 Signed-off-by: Paul Fagerburg BUG=b:132148525 BRANCH=none TEST=cd ~/trunk/src/platform/ec; make BOARD=kohaku -j Change-Id: I125ebbd521c57fd616151766fba0ea5e9eda2a9a Reviewed-on: https://chromium-review.googlesource.com/1600299 Commit-Ready: Paul Fagerburg Tested-by: Paul Fagerburg Reviewed-by: Scott Collyer --- board/kohaku/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/kohaku/gpio.inc b/board/kohaku/gpio.inc index 9e0e06fa30..c85e080125 100644 --- a/board/kohaku/gpio.inc +++ b/board/kohaku/gpio.inc @@ -39,7 +39,7 @@ GPIO_INT(USB_C1_BC12_INT_ODL, PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(C, 5), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ -- cgit v1.2.1