From 78a407f0a15d1bfc7fa098751e292bc7e7b190a3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 19 Feb 2018 17:30:43 -0800 Subject: npcx: Set ESPI_MAXFREQ based on FMCLK value According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should be decided based on the value of FMCLK. Since we are setting FMCLK to 30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz. This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK. BUG=b:73504527 BRANCH=fizz? TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran some reboot tests to ensure that there is no regression in boot time. Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35 Signed-off-by: Furquan Shaikh Reviewed-on: https://chromium-review.googlesource.com/925843 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aseda Aboagye Reviewed-by: Aaron Durbin Reviewed-by: Mulin Chao Reviewed-by: caveh jalali Reviewed-by: Vincent Palatin --- chip/npcx/registers.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index d451eb04c9..9bca32e82f 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -9,6 +9,8 @@ #define __CROS_EC_REGISTERS_H #include "common.h" +#include "clock_chip.h" + /******************************************************************************/ /* * Macro Functions @@ -1673,9 +1675,23 @@ enum { }; #if defined(CHIP_FAMILY_NPCX5) + +#if (FMCLK <= 33000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#elif (FMCLK <= 48000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#else #define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_66 +#endif + #elif defined(CHIP_FAMILY_NPCX7) + +#if (FMCLK <= 33000000) +#define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_33 +#else #define NPCX_ESPI_MAXFREQ_MAX NPCX_ESPI_MAXFREQ_50 +#endif + #else #error "Please define NPCX_ESPI_MAXFREQ_MAX for your chip." #endif -- cgit v1.2.1