From 7999cc115b95dc918ec6a89d4e0f4b55728557d7 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Thu, 2 Sep 2021 15:21:46 +0800 Subject: it83xx/riscv: Ensure IER has been disabled before enabling CPU interrupt This CL read EC's IER one time after configured. The load operation will ensure chip-level's interrupt has been disabled before enabling CPU interrupt. BRANCH=asurada, icarus BUG=b:179206540 TEST=create stress test on it8xxx2 evb: - Loop calling task_disable_irq() and task_enable_irq() to enable and disable IRQ 13 (keyboard KSI interrupt). - Toggle KSI continuously. Without the patch, EC will hit IRQ 0 issue in two seconds. Signed-off-by: Dino Li Change-Id: I56bad182bd101d45b00368083b60aabbd9fb8bdb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139652 Reviewed-by: Eric Yilun Lin Commit-Queue: Eric Yilun Lin --- chip/it83xx/irq.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index c2564c05a3..308fa5b2e7 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -122,8 +122,16 @@ void chip_disable_irq(int irq) int bit = irq % 8; /* SOC's interrupts share CPU machine-mode external interrupt */ - if (IS_ENABLED(CHIP_CORE_RISCV)) + if (IS_ENABLED(CHIP_CORE_RISCV)) { + volatile uint8_t _ier __unused; + IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); + /* + * This load operation will guarantee the above modification of + * EC's register can be seen by any following instructions. + */ + _ier = IT83XX_INTC_REG(irq_groups[group].ier_off); + } /* SOC's interrupts use CPU HW interrupt 2 ~ 15 */ if (IS_ENABLED(CHIP_CORE_NDS32)) -- cgit v1.2.1