From 93ff538d4c637860e19130c8d47f26081eb8a35c Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Thu, 5 Dec 2019 15:32:00 -0800 Subject: volteer: Keep RSMRST# pin low at init Keeping the RSMRST# pin is low at init based on the TGL PDG power sequence Timing Diagram. BUG=b:145767544 BRANCH=none TEST=Verified on scope, RSMRST# pin is low at init Change-Id: Ia5d5c76ce3f173d1c283da706dd1113ce1dad550 Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954875 Reviewed-by: Keith Short --- board/volteer/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/volteer/gpio.inc b/board/volteer/gpio.inc index d18e272f12..5f6c213adf 100644 --- a/board/volteer/gpio.inc +++ b/board/volteer/gpio.inc @@ -75,7 +75,7 @@ GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | /* AP/PCH Signals */ GPIO(EC_PCH_SYS_PWROK, PIN(3, 7), GPIO_OUT_LOW) -GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_HIGH) /* TODO - b/140950085 - implement TGL sequencing requirement */ +GPIO(EC_PCH_RSMRST_ODL, PIN(A, 6), GPIO_ODR_LOW) /* TODO - b/140950085 - implement TGL sequencing requirement */ GPIO(EC_PCH_PWR_BTN_ODL, PIN(C, 1), GPIO_ODR_HIGH) GPIO(EC_PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) GPIO(EC_PCH_WAKE_ODL, PIN(7, 4), GPIO_ODR_HIGH) -- cgit v1.2.1