From 946921a974542b9e00fa412ae03df59f8fa82d84 Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Thu, 8 Sep 2016 09:56:47 -0700 Subject: npcx: rtc: Write RTC reg twice to ensure non-volatility TTC must be written twice, otherwise the value will be lost on EC reset, even if VBAT stays stable. BUG=chrome-os-partner:57010 BRANCH=None TEST=On kevin, run 'rtc set 55555' then trigger cold reset through servo. Run 'rtc' on subsequent boot and verify timing ticks did not reset to zero. Change-Id: If05b698e75eece5f8879a109b98886b547eb71a4 Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/382654 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Aseda Aboagye --- chip/npcx/system.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/chip/npcx/system.c b/chip/npcx/system.c index f6f4804c35..babfbe15a3 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -26,8 +26,8 @@ #define HIBERNATE_WAKE_MTC (1 << 0) /* MTC alarm */ #define HIBERNATE_WAKE_PIN (1 << 1) /* Wake pin */ -/* equivalent to 250us according to 48MHz core clock */ -#define MTC_TTC_LOAD_DELAY 1500 +/* Delay after writing TTC for value to latch */ +#define MTC_TTC_LOAD_DELAY_US 250 #define MTC_ALARM_MASK ((1 << 25) - 1) #define MTC_WUI_GROUP MIWU_GROUP_4 #define MTC_WUI_MASK MASK_PIN7 @@ -141,14 +141,14 @@ uint32_t system_get_rtc_sec(void) void system_set_rtc(uint32_t seconds) { - volatile uint16_t __i; - - /* Set MTC counter unit:seconds */ + /* + * Set MTC counter unit:seconds, write twice to ensure values + * latch to NVMem. + */ NPCX_TTC = seconds; - - /* Wait till clock is readable */ - for (__i = 0; __i < MTC_TTC_LOAD_DELAY; ++__i) - ; + udelay(MTC_TTC_LOAD_DELAY_US); + NPCX_TTC = seconds; + udelay(MTC_TTC_LOAD_DELAY_US); } /* Check reset cause */ -- cgit v1.2.1