From 9cd1dcc3fd581100d28444c087f3df0ca8a8e0d6 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Tue, 18 Apr 2017 11:10:41 +0800 Subject: npcx: Introduce npcx7 series ec chip definitions and configurations. This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye Reviewed-by: Randall Spangler --- chip/npcx/build.mk | 5 +++ chip/npcx/config_chip-npcx5.h | 66 +++++++++++++++++++++++++++++++++++++++ chip/npcx/config_chip-npcx7.h | 69 +++++++++++++++++++++++++++++++++++++++++ chip/npcx/config_chip.h | 45 ++++++--------------------- chip/npcx/config_flash_layout.h | 5 +++ 5 files changed, 154 insertions(+), 36 deletions(-) create mode 100644 chip/npcx/config_chip-npcx5.h create mode 100644 chip/npcx/config_chip-npcx7.h diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 2814366ffb..d5047237e9 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -11,6 +11,11 @@ CORE:=cortex-m # Allow the full Cortex-M4 instruction set CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4 +# Assign default CHIP_FAMILY as npcx5 for old boards used npcx5 series +ifeq ($(CHIP_FAMILY),) +CHIP_FAMILY:=npcx5 +endif + # Required chip modules chip-y=header.o clock.o gpio.o hwtimer.o jtag.o system.o uart.o diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h new file mode 100644 index 0000000000..71c8d8d7af --- /dev/null +++ b/chip/npcx/config_chip-npcx5.h @@ -0,0 +1,66 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H +#define __CROS_EC_CONFIG_CHIP_NPCX5_H + +/* + * NPCX5 Series Device-Specific Information + * Ex. NPCX5-M-N-G + * @param M: 7: 132-pins package, 8: 128-pins package + * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size + * @param G: Google EC. + */ + +/*****************************************************************************/ +/* Hardware features */ +/* + * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one + * additional port. + */ +#define CONFIG_I2C_MULTI_PORT_CONTROLLER +/* Number of I2C controllers */ +#define I2C_CONTROLLER_COUNT 4 +/* Number of I2C ports */ +#define I2C_PORT_COUNT 5 + +/*****************************************************************************/ +/* Memory mapping */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +#define CONFIG_RAM_SIZE (0x0008000 - NPCX_BTRAM_SIZE) /* 30KB data ram */ +#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ + +/* Use chip variant to specify the size and start address of program memory */ +#if defined(CHIP_VARIANT_NPCX5M5G) +/* 96KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024) +/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 +#elif defined(CHIP_VARIANT_NPCX5M6G) +/* 224KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024) +/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 +#else +#error "Unsupported chip variant" +#endif + +/* Total RAM size checking for npcx ec */ +#define NPCX_RAM_SIZE (NPCX_BTRAM_SIZE + CONFIG_RAM_SIZE + \ + NPCX_PROGRAM_MEMORY_SIZE) +#if defined(CHIP_VARIANT_NPCX5M5G) +/* 128KB RAM in NPCX5M5G */ +#if (NPCX_RAM_SIZE != 0x20000) +#error "Wrong memory mapping layout for NPCX5M5G" +#endif +#elif defined(CHIP_VARIANT_NPCX5M6G) +/* 256KB RAM in NPCX5M6G */ +#if (NPCX_RAM_SIZE != 0x40000) +#error "Wrong memory mapping layout for NPCX5M6G" +#endif +#endif + +#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */ diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h new file mode 100644 index 0000000000..54b5feca6b --- /dev/null +++ b/chip/npcx/config_chip-npcx7.h @@ -0,0 +1,69 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CONFIG_CHIP_NPCX7_H +#define __CROS_EC_CONFIG_CHIP_NPCX7_H + +/* + * NPCX7 Series Device-Specific Information + * Ex. NPCX7-M-N-G/K/F + * @param M: 9: 144-pins package + * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size + * @param G/K/F: Google EC depends on specific features. + */ + +/*****************************************************************************/ +/* Hardware features */ + +/* The optional hardware features depend on chip variant */ +#if defined(CHIP_VARIANT_NPCX7M6F) +#define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ +#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ +#define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ +#endif + +/* + * Number of I2C controllers. Controller 4/5/6 has 2 ports, so the chip has + * three additional ports. + */ +#define CONFIG_I2C_MULTI_PORT_CONTROLLER +/* Number of I2C controllers */ +#define I2C_CONTROLLER_COUNT 8 +/* Number of I2C ports */ +#ifdef NPCX_PSL_MODE_SUPPORT +#define I2C_PORT_COUNT 10 +#else +#define I2C_PORT_COUNT 11 +#endif + +/*****************************************************************************/ +/* Memory mapping */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* no low power ram in npcx7 series */ + +/* Use chip variant to specify the size and start address of program memory */ +#if defined(CHIP_VARIANT_NPCX7M6F) +/* 62KB data ram */ +#define CONFIG_RAM_SIZE (0x00010000 - NPCX_BTRAM_SIZE) +/* 192KB RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) +/* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#else +#error "Unsupported chip variant" +#endif + +/* Total RAM size checking for npcx ec */ +#define NPCX_RAM_SIZE (NPCX_BTRAM_SIZE + CONFIG_RAM_SIZE + \ + NPCX_PROGRAM_MEMORY_SIZE) +#if defined(CHIP_VARIANT_NPCX7M6F) +/* 256KB RAM in NPCX7M6F */ +#if (NPCX_RAM_SIZE != 0x40000) +#error "Wrong memory mapping layout for NPCX7M6F" +#endif +#endif + +#endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */ diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 1442a58d50..90bfc9ab44 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -9,6 +9,15 @@ /* CPU core BFD configuration */ #include "core/cortex-m/config_core.h" +/* Features depend on chip family */ +#if defined(CHIP_FAMILY_NPCX5) +#include "config_chip-npcx5.h" +#elif defined(CHIP_FAMILY_NPCX7) +#include "config_chip-npcx7.h" +#else +#error "Unsupported chip family" +#endif + /* 32k hz internal oscillator frequency (FRCLK) */ #define INT_32K_CLOCK 32768 @@ -26,42 +35,6 @@ #define HOOK_TICK_INTERVAL_MS 200 #define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) -/* - * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one - * additional port. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER -/* Number of I2C controllers */ -#define I2C_CONTROLLER_COUNT 4 -/* Number of I2C ports */ -#define I2C_PORT_COUNT 5 - - -/* Number of PWM ports */ -#define PWM_COUNT 8 - -/*****************************************************************************/ -/* Memory mapping */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ - -/* Use chip variant to specify the size and start address of program memory */ -#if defined(CHIP_VARIANT_NPCX5M5G) -/* 96KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024) -/* program memory base address for 128KB RAM */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 -#elif defined(CHIP_VARIANT_NPCX5M6G) -/* 224KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024) -/* program memory base address for 256KB RAM */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 -#else -#error "Unsupported chip variant" -#endif - /* System stack size */ #define CONFIG_STACK_SIZE 1024 diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index b79eed3e17..af00499006 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -30,6 +30,11 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#elif defined(CHIP_VARIANT_NPCX7M6F) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 #else #error "Unsupported chip variant" #endif -- cgit v1.2.1