From a0f25e398ec74b455953833a5e73bd0e8f71feed Mon Sep 17 00:00:00 2001 From: CHLin Date: Wed, 10 Jan 2018 11:29:45 +0800 Subject: npcx7: Add definition/configuration for npcx7m6xb/npcx7m7w In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin Tested-by: CH Lin Reviewed-by: Randall Spangler --- chip/npcx/build.mk | 1 + chip/npcx/config_chip-npcx7.h | 33 +++++++++++++++++++++++++-------- chip/npcx/config_flash_layout.h | 8 +++++++- chip/npcx/registers.h | 9 ++++++++- chip/npcx/wov.c | 10 ++++++++++ include/config.h | 3 +++ 6 files changed, 54 insertions(+), 10 deletions(-) create mode 100644 chip/npcx/wov.c diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index ff65c95d1e..2cd4d087c2 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -34,6 +34,7 @@ chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_SPI)+=spi.o chip-$(CONFIG_WATCHDOG)+=watchdog.o chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o +chip-$(CONFIG_WAKE_ON_VOICE)+=wov.o # spi monitor program fw for openocd and UUT(UART Update Tool) npcx-monitor-fw=chip/npcx/spiflashfw/npcx_monitor diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 2506f0f558..d2cf002ee2 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -18,12 +18,17 @@ /* Hardware features */ /* The optional hardware features depend on chip variant */ -#if defined(CHIP_VARIANT_NPCX7M6F) +#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M7W) || \ + defined(CHIP_VARIANT_NPCX7M6XB) #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ #define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #endif +#ifdef CHIP_VARIANT_NPCX7M7W +#define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */ +#endif + /* * Number of I2C controllers. Controller 4/5/6 has 2 ports, so the chip has * three additional ports. @@ -43,30 +48,42 @@ /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define NPCX_BTRAM_SIZE 0x400 /* 1KB data ram used by booter. */ #define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +/* 63KB data RAM */ +#define CONFIG_DATA_RAM_SIZE 0x00010000 +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) /* no low power ram in npcx7 series */ /* Use chip variant to specify the size and start address of program memory */ -#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) -/* 62KB data ram */ -#define CONFIG_DATA_RAM_SIZE 0x00010000 -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) || \ + defined(CHIP_VARIANT_NPCX7M6XB) /* 192KB RAM for FW code */ #define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) /* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */ #define CONFIG_PROGRAM_MEMORY_BASE 0x10090000 +#elif defined(CHIP_VARIANT_NPCX7M7W) +/* 320 RAM for FW code */ +#define NPCX_PROGRAM_MEMORY_SIZE (320 * 1024) +/* program memory base address for 320KB Code RAM (ie. 0x100C0000 - 320KB) */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x10070000 #else #error "Unsupported chip variant" #endif /* Total RAM size checking for npcx ec */ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) -#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) -/* 256KB RAM in NPCX7M6F */ +#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) || \ + defined(CHIP_VARIANT_NPCX7M6XB) +/* 256KB RAM in NPCX7M6F/NPCX7M6G/NPCX7M6XB */ #if (NPCX_RAM_SIZE != 0x40000) #error "Wrong memory mapping layout for NPCX7M6F" #endif +#elif defined(CHIP_VARIANT_NPCX7M7W) +/* 384KB RAM in NPCX7M7W */ +#if (NPCX_RAM_SIZE != 0x60000) +#error "Wrong memory mapping layout for NPCX7M6F" +#endif #endif #endif /* __CROS_EC_CONFIG_CHIP_NPCX7_H */ diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h index 46215655c7..382f807e1a 100644 --- a/chip/npcx/config_flash_layout.h +++ b/chip/npcx/config_flash_layout.h @@ -30,11 +30,17 @@ #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 -#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) +#elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6G) || \ + defined(CHIP_VARIANT_NPCX7M6XB) #define CONFIG_EC_PROTECTED_STORAGE_OFF 0 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_OFF 0x40000 #define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x40000 +#elif defined(CHIP_VARIANT_NPCX7M7W) +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0x80000 +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x80000 #else #error "Unsupported chip variant" #endif diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 929212f8e1..0e12e5f7f4 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -823,7 +823,10 @@ enum { #define NPCX_ENIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x003) #define NPCX_DISIDL_CTL REG8(NPCX_PMC_BASE_ADDR + 0x004) #define NPCX_DISIDL_CTL1 REG8(NPCX_PMC_BASE_ADDR + 0x005) -#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PMC_BASE_ADDR + 0x008 + offset) +#define NPCX_PWDWN_CTL_ADDR(offset) (((offset) < 6) ? \ + (NPCX_PMC_BASE_ADDR + 0x008 + (offset)) : \ + (NPCX_PMC_BASE_ADDR + 0x024)) +#define NPCX_PWDWN_CTL(offset) REG8(NPCX_PWDWN_CTL_ADDR(offset)) #if defined(CHIP_FAMILY_NPCX7) #define NPCX_RAM_PD(offset) REG8(NPCX_PMC_BASE_ADDR + 0x020 + offset) #endif @@ -1150,7 +1153,11 @@ enum PM_CHANNEL_T { /* BBRAM register fields */ #define NPCX_BKUP_STS_IBBR 7 +#if defined(CHIP_VARIANT_NPCX7M7W) || defined(CHIP_VARIANT_NPCX7M6XB) +#define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ +#else #define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ +#endif /******************************************************************************/ /* Timer Watch Dog (TWD) Registers */ diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c new file mode 100644 index 0000000000..6ea921e076 --- /dev/null +++ b/chip/npcx/wov.c @@ -0,0 +1,10 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" + +#ifndef NPCX_WOV_SUPPORT +#error "Do not enable CONFIG_WAKE_ON_VOICE if npcx ec doesn't support WOV !" +#endif diff --git a/include/config.h b/include/config.h index 50f84314ed..5126164767 100644 --- a/include/config.h +++ b/include/config.h @@ -3065,6 +3065,9 @@ /* WiFi power control signal is active-low. */ #undef CONFIG_WLAN_POWER_ACTIVE_LOW +/* Support Wake-on-Voice */ +#undef CONFIG_WAKE_ON_VOICE + /* * Write protect signal is active-high. If this is defined, there must be a * GPIO named GPIO_WP; if not defined, there must be a GPIO names GPIO_WP_L. -- cgit v1.2.1