From c26a242e947a110ea3cf0c43d8274eebb9aaeb5a Mon Sep 17 00:00:00 2001 From: Randall Spangler Date: Thu, 6 Dec 2012 15:46:28 -0800 Subject: Increase cold reset hibernate time to 200ms The hardware fix for issue 16600 adds RC delays to ENABLE_5VALW, so that +5VALW stays on during a warm reset of the EC. In the worst case, +5VALW will drop around 150ms, which could then move the +3VALW glitch right into the time frame where the EC is booting following hibernate. Increase the cold reset hibernate time from 150ms to 200ms. This ensures that +5VALW has dropped before the EC comes out of hibernate. BUG=chrome-os-partner:16600 BRANCH=link TEST=manual From the EC console, 'reboot cold' a bunch of times. The system shouldn't hang. (Alternately, you can 'ectool reboot_ec cold' a bunch of times) Change-Id: I4bebdb552b8e917c6345badd6efb68b10d7d1f86 Signed-off-by: Randall Spangler Reviewed-on: https://gerrit.chromium.org/gerrit/39340 Reviewed-by: Bill Richardson --- chip/lm4/system.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/chip/lm4/system.c b/chip/lm4/system.c index b6e37ca0ec..bbe70e6793 100644 --- a/chip/lm4/system.c +++ b/chip/lm4/system.c @@ -35,9 +35,9 @@ enum hibdata_index { /* * Time to hibernate to trigger a power-on reset. 50 ms is sufficient for the * EC itself, but we need a longer delay to ensure the rest of the components - * on the same power rail are reset. + * on the same power rail are reset and 5VALW has dropped. */ -#define HIB_RESET_USEC 150000 +#define HIB_RESET_USEC 200000 /** * Wait for a write to commit to a hibernate register. -- cgit v1.2.1