From cb4f3ca409758491054bdcf56a76fd48945e6c2e Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Thu, 17 Nov 2016 12:56:13 -0800 Subject: clock: Fix clock_wait_cycles() asm The 'cycles' register will be clobbered by our macro, so it must be specified as an output operand that may also be used as input. BUG=chrome-os-partner:60000 BRANCH=gru,strago,glados TEST=Build + burn wheatley, verify alignment exception is not encountered on boot. Also verify produced assembly is still correct: 100a89a6: 2303 movs r3, #3 100a89a8: 3b01 subs r3, #1 100a89aa: d1fd bne.n 100a89a8 Signed-off-by: Shawn Nematbakhsh Change-Id: I1be03a006967aed6970dbac5d98a19a31e0b7d49 Reviewed-on: https://chromium-review.googlesource.com/412350 --- chip/lm4/clock.c | 4 ++-- chip/mec1322/clock.c | 4 ++-- chip/npcx/clock.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/chip/lm4/clock.c b/chip/lm4/clock.c index b8029f5d27..d86a31230c 100644 --- a/chip/lm4/clock.c +++ b/chip/lm4/clock.c @@ -140,8 +140,8 @@ void clock_enable_pll(int enable, int notify) void clock_wait_cycles(uint32_t cycles) { - asm("1: subs %0, #1\n" - " bne 1b\n" :: "r"(cycles)); + asm volatile("1: subs %0, #1\n" + " bne 1b\n" : "+r"(cycles)); } int clock_get_freq(void) diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index 9cef11686f..c5ce698b2a 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -45,8 +45,8 @@ static int freq = 48000000; void clock_wait_cycles(uint32_t cycles) { - asm("1: subs %0, #1\n" - " bne 1b\n" :: "r"(cycles)); + asm volatile("1: subs %0, #1\n" + " bne 1b\n" : "+r"(cycles)); } int clock_get_freq(void) diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index c59516043b..5cbd54cf11 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -174,8 +174,8 @@ int clock_get_apb2_freq(void) */ void clock_wait_cycles(uint32_t cycles) { - asm("1: subs %0, #1\n" - " bne 1b\n" : : "r"(cycles)); + asm volatile("1: subs %0, #1\n" + " bne 1b\n" : "+r"(cycles)); } #ifdef CONFIG_LOW_POWER_IDLE -- cgit v1.2.1