From 926f0b68e18c4fc5c8ed48efe2bb7640cb8a391c Mon Sep 17 00:00:00 2001 From: ben chen Date: Fri, 12 May 2023 16:50:22 +0800 Subject: Craask: define LED behavior at STATE_DISCHARGE_S0_BAT_LOW STATE_DISCHARGE_S0_BAT_LOW: Blue on BUG=b:282116750 TEST=check LED behavior while SOC < 10% in battery mode. Change-Id: I57487200de2360dfa34cecda8a99ab1c008d2758 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4525880 Reviewed-by: Ben Chen Tested-by: Ben Chen Commit-Queue: Shou-Chieh Hsu Reviewed-by: Shou-Chieh Hsu --- zephyr/program/nissa/craask/src/led.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/program/nissa/craask/src/led.c b/zephyr/program/nissa/craask/src/led.c index 0af0202cf4..b3aefa3ab2 100644 --- a/zephyr/program/nissa/craask/src/led.c +++ b/zephyr/program/nissa/craask/src/led.c @@ -22,7 +22,7 @@ __override struct led_descriptor LED_INDEFINITE } }, [STATE_DISCHARGE_S0] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, - [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_AMBER, + [STATE_DISCHARGE_S0_BAT_LOW] = { { EC_LED_COLOR_BLUE, LED_INDEFINITE } }, [STATE_DISCHARGE_S3] = { { EC_LED_COLOR_AMBER, 1 * LED_ONE_SEC }, -- cgit v1.2.1 From e89f731318700b04bc3d4872d88223d97c2e0270 Mon Sep 17 00:00:00 2001 From: wangganxiang Date: Tue, 9 May 2023 16:23:21 +0800 Subject: starmie: Improve RT1739 dead battery voltage issue Add RT1739 initialization during EC boot. This modification is optimized for dead battery voltage issues. BUG=b:281606949 TEST=zmake build starmie The board can power on normally under AC only mode. Change-Id: I1843b9bce231bc730ad1c4ccb69d74fe3d7beb65 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4516061 Reviewed-by: Mike Lee Commit-Queue: Ganxiang Wang Reviewed-by: Sung-Chi Li Tested-by: Ganxiang Wang --- driver/ppc/rt1739.c | 2 +- driver/ppc/rt1739.h | 2 ++ zephyr/program/corsola/starmie/src/ppc.c | 8 ++++++++ 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/driver/ppc/rt1739.c b/driver/ppc/rt1739.c index ffd7760986..4679290b67 100644 --- a/driver/ppc/rt1739.c +++ b/driver/ppc/rt1739.c @@ -273,7 +273,7 @@ static int rt1739_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp) return write_reg(port, RT1739_REG_VBUS_OC_SETTING, reg); } -static int rt1739_init(int port) +int rt1739_init(int port) { int device_id, oc_setting, sys_ctrl, vbus_switch_ctrl; bool batt_connected = false; diff --git a/driver/ppc/rt1739.h b/driver/ppc/rt1739.h index f4c5e44354..48256da202 100644 --- a/driver/ppc/rt1739.h +++ b/driver/ppc/rt1739.h @@ -134,4 +134,6 @@ extern const struct bc12_drv rt1739_bc12_drv; void rt1739_interrupt(int port); +int rt1739_init(int port); + #endif /* defined(__CROS_EC_PPC_RT1739_H) */ diff --git a/zephyr/program/corsola/starmie/src/ppc.c b/zephyr/program/corsola/starmie/src/ppc.c index 8c1dc2fe7f..505da06473 100644 --- a/zephyr/program/corsola/starmie/src/ppc.c +++ b/zephyr/program/corsola/starmie/src/ppc.c @@ -27,3 +27,11 @@ void ppc_interrupt(enum gpio_signal signal) ppc_chips[0].drv->interrupt(0); } } + +static int set_rt1739(void) +{ + rt1739_init(0); + return 0; +} + +SYS_INIT(set_rt1739, POST_KERNEL, 61); -- cgit v1.2.1 From cebec588aa5be0671424ea484527a68682a0626e Mon Sep 17 00:00:00 2001 From: michael5_chen1 Date: Thu, 11 May 2023 08:49:27 +0800 Subject: [marasov] Enable CONFIG_USB_PD_VBUS_DETECT_PPC Denpend on HW design, the VBUS control by PPC. Enable CONFIG_USB_PD_VBUS_DETECT_PPC. Disable CONFIG_USB_PD_VBUS_DETECT_TCPCl. BUG=b:277171675 TEST=manual C1: Plug AC through HUB pass (10/10) C1: Plug AC pass (10/10) C0: Plug AC through HUB Pass (10/10) C0: PLug AC pass (10/10) Change-Id: Id91f0aef5e5e24e969c9a50934d821a491d9146b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4520030 Reviewed-by: Michael5 Chen Code-Coverage: Kyle Lin Reviewed-by: Kyle Lin Tested-by: Michael5 Chen Commit-Queue: Kyle Lin --- board/marasov/board.h | 2 ++ board/marasov/usbc_config.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/board/marasov/board.h b/board/marasov/board.h index f386087d65..b34e69224b 100644 --- a/board/marasov/board.h +++ b/board/marasov/board.h @@ -39,6 +39,8 @@ #define CONFIG_IO_EXPANDER_PORT_COUNT 1 #define CONFIG_USB_PD_FRS_PPC +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#undef CONFIG_USB_PD_VBUS_DETECT_TCPC #define CONFIG_USB_PD_TCPM_PS8815 #define CONFIG_USB_PD_TCPM_PS8815_FORCE_DID diff --git a/board/marasov/usbc_config.c b/board/marasov/usbc_config.c index b32421969c..2fa5efea5f 100644 --- a/board/marasov/usbc_config.c +++ b/board/marasov/usbc_config.c @@ -318,3 +318,10 @@ __override bool board_is_dts_port(int port) { return port == USBC_PORT_C0; } + +#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC +int pd_snk_is_vbus_provided(int port) +{ + return ppc_is_vbus_present(port); +} +#endif -- cgit v1.2.1 From 888cbb55c3c1d1169bdf9f541b0fd31054ff1bc4 Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Wed, 10 May 2023 20:35:35 +0800 Subject: omnigul: Modify LED behavior Modify LED behavior to meet SPEC. S3(discharge): Amber on 1 sec, off 3 sec. S5(discharge): LED off. Battery Error: Amber on 1 sec, off 1 sec. BUG=b:281786726, b:281785649, b:281782326 TEST=test LED behavior meet SPEC. Change-Id: I8e99dfe1d3d415fd5182e494d57e1a02b5c1c59e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4521358 Code-Coverage: Kyle Lin Tested-by: Logan Liao Reviewed-by: Josh Tsai Commit-Queue: Kyle Lin Reviewed-by: Kyle Lin Reviewed-by: Logan Liao --- board/omnigul/board.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/board/omnigul/board.h b/board/omnigul/board.h index 76e5c8656f..220d993667 100644 --- a/board/omnigul/board.h +++ b/board/omnigul/board.h @@ -33,10 +33,12 @@ #undef CONFIG_LED_PWM_SOC_ON_COLOR #undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR #undef CONFIG_LED_PWM_LOW_BATT_COLOR +#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR #define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_BLUE #define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE -#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_BLUE +#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_AMBER #define CONFIG_LED_PWM_LOW_BATT_COLOR EC_LED_COLOR_AMBER +#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER /* Sensors */ #define CONFIG_ACCELGYRO_LSM6DSO /* Base accel */ -- cgit v1.2.1 From 9a21e1e51a47b5adff47990e75e62661e9b33827 Mon Sep 17 00:00:00 2001 From: Firas Sammoura Date: Fri, 10 Mar 2023 18:59:06 +0000 Subject: ec: Enable unaligned access for cortex-m Enable unaligned access for cortext-m and. Add a unit test to validate that unaligned access runs properly on both bloonchipper and dartmonkey. Add benchmarks to measure the speed gain between aligned and unaligned access. BRANCH=none BUG=b:239254184 TEST=test/run_device_tests.py -b dartmonkey -t unaligned_access TEST=test/run_device_tests.py -b bloonchipper -t unaligned_access Change-Id: I7d75433e6b7b33d7c82ad740dc85a8646d891c6a Signed-off-by: Firas Sammoura Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4327795 Reviewed-by: Bobby Casey Reviewed-by: Mike Frysinger --- board/hatch_fp/build.mk | 1 + board/nocturne_fp/build.mk | 1 + core/cortex-m/cpu.c | 4 +- test/build.mk | 1 + test/run_device_tests.py | 1 + test/unaligned_access.cc | 157 +++++++++++++++++++++++++++++++++++++++++ test/unaligned_access.tasklist | 9 +++ 7 files changed, 172 insertions(+), 2 deletions(-) create mode 100644 test/unaligned_access.cc create mode 100644 test/unaligned_access.tasklist diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk index 7ded3aeb6a..5e7af56ae2 100644 --- a/board/hatch_fp/build.mk +++ b/board/hatch_fp/build.mk @@ -69,6 +69,7 @@ test-list-y=\ timer \ timer_dos \ tpm_seed_clear \ + unaligned_access \ utils \ utils_str \ diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk index dc99c72f85..e36309c4f0 100644 --- a/board/nocturne_fp/build.mk +++ b/board/nocturne_fp/build.mk @@ -68,6 +68,7 @@ test-list-y=\ timer \ timer_dos \ tpm_seed_clear \ + unaligned_access \ utils \ utils_str \ diff --git a/core/cortex-m/cpu.c b/core/cortex-m/cpu.c index 5a882bb532..adcdb4e1a3 100644 --- a/core/cortex-m/cpu.c +++ b/core/cortex-m/cpu.c @@ -15,8 +15,8 @@ void cpu_init(void) { - /* Catch divide by 0 and unaligned access */ - CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP | CPU_NVIC_CCR_UNALIGN_TRAP; + /* Catch divide by 0 */ + CPU_NVIC_CCR |= CPU_NVIC_CCR_DIV_0_TRAP; /* Enable reporting of memory faults, bus faults and usage faults */ CPU_NVIC_SHCSR |= CPU_NVIC_SHCSR_MEMFAULTENA | diff --git a/test/build.mk b/test/build.mk index 2d2f9341a3..d948fd5f6e 100644 --- a/test/build.mk +++ b/test/build.mk @@ -277,6 +277,7 @@ timer_calib-y=timer_calib.o timer_dos-y=timer_dos.o timer-y=timer.o tpm_seed_clear-y=tpm_seed_clear.o +unaligned_access-y=unaligned_access.o uptime-y=uptime.o usb_common-y=usb_common_test.o fake_battery.o usb_pd_int-y=usb_pd_int.o diff --git a/test/run_device_tests.py b/test/run_device_tests.py index f385441f6d..dc454527e7 100755 --- a/test/run_device_tests.py +++ b/test/run_device_tests.py @@ -332,6 +332,7 @@ class AllTests: TestConfig(test_name="timer"), TestConfig(test_name="timer_dos"), TestConfig(test_name="tpm_seed_clear"), + TestConfig(test_name="unaligned_access"), TestConfig(test_name="utils", timeout_secs=20), TestConfig(test_name="utils_str"), ] diff --git a/test/unaligned_access.cc b/test/unaligned_access.cc new file mode 100644 index 0000000000..f3dc99d432 --- /dev/null +++ b/test/unaligned_access.cc @@ -0,0 +1,157 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * Test if unaligned access works properly + */ + +#include "common.h" +#include "console.h" +#include "test_util.h" + +extern "C" { +#include "shared_mem.h" +#include "timer.h" +} + +#include +#include +#include + +test_static int test_unaligned_access() +{ + /* This is equivalent to {0xff, 0x09, 0x04, 0x06, 0x04, 0x06, 0x07, + * 0xed, 0x0a, 0x0b, 0x0d, 0x38, 0xbd, 0x57, 0x59} */ + alignas(int32_t) constexpr std::array test_array = { + -1, 9, 4, 6, 4, 6, 7, -19, 10, 11, 13, 56, -67, 87, 89 + }; + + constexpr std::array expected_results = { + 0x060409ff, + 0x04060409, + 0x06040604, + 0x07060406, + static_cast(0xed070604), + 0x0aed0706, + 0x0b0aed07, + 0x0d0b0aed, + 0x380d0b0a, + static_cast(0xbd380d0b), + 0x57bd380d, + 0x5957bd38 + }; + + /* If i % 4 = 0, we have an aligned access. Otherwise, it is + unaligned access. */ + for (int i = 0; i < expected_results.size(); ++i) { + const int32_t *test_array_ptr = + reinterpret_cast(test_array.data() + + i); + + TEST_EQ(*test_array_ptr, expected_results[i], "0x%08x"); + } + + return EC_SUCCESS; +} + +test_static int benchmark_unaligned_access_memcpy() +{ + int i; + timestamp_t t0, t1, t2, t3; + char *buf; + const int buf_size = 1000; + const int len = 400; + const int dest_offset = 500; + const int iteration = 1000; + + TEST_ASSERT(shared_mem_acquire(buf_size, &buf) == EC_SUCCESS); + + for (i = 0; i < len; ++i) + buf[i] = i & 0x7f; + for (i = len; i < buf_size; ++i) + buf[i] = 0; + + t0 = get_time(); + for (i = 0; i < iteration; ++i) { + memcpy(buf + dest_offset + 1, buf, len); /* unaligned */ + } + t1 = get_time(); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset + 1, buf, len); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); + + t2 = get_time(); + for (i = 0; i < iteration; ++i) { + memcpy(buf + dest_offset, buf, len); /* aligned */ + } + t3 = get_time(); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); + TEST_ASSERT_ARRAY_EQ(buf + dest_offset, buf, len); + return EC_SUCCESS; +} + +test_static int benchmark_unaligned_access_array() +{ + timestamp_t t0, t1, t2, t3; + const int iteration = 1000; + + alignas(int32_t) std::array test_array_1; + std::array test_array_2; + constexpr std::array test_array_3 = { + 67305985, 134678021, 202050057, 269422093, 336794129, + 404166165, 471538201, 538910237, 606282273, 673654309, + 741026345, 808398381, 875770417, 943142453, 1010514489, + 1077886525, 1145258561, 1212630597, 1280002633, 1347374669 + }; + constexpr std::array test_array_4 = { + 50462976, 117835012, 185207048, 252579084, 319951120, + 387323156, 454695192, 522067228, 589439264, 656811300, + 724183336, 791555372, 858927408, 926299444, 993671480, + 1061043516, 1128415552, 1195787588, 1263159624, 1330531660 + }; + + for (int i = 0; i < test_array_1.size(); ++i) { + test_array_1[i] = static_cast(i); + } + + t0 = get_time(); + for (int t = 0; t < iteration; ++t) { + const int32_t *test_array_1_ptr = + reinterpret_cast(test_array_1.data() + + 1); + + for (int i = 0; i < test_array_2.size(); ++i) { + test_array_2[i] = (*test_array_1_ptr++); /* unaligned */ + } + TEST_ASSERT_ARRAY_EQ(test_array_2.data(), test_array_3.data(), + test_array_2.size()); + } + t1 = get_time(); + ccprintf(" (speed gain: %" PRId64 " ->", t1.val - t0.val); + + t2 = get_time(); + for (int t = 0; t < iteration; ++t) { + const int32_t *test_array_1_ptr = + reinterpret_cast(test_array_1.data()); + + for (int i = 0; i < test_array_2.size(); ++i) { + test_array_2[i] = (*test_array_1_ptr++); /* aligned */ + } + TEST_ASSERT_ARRAY_EQ(test_array_2.data(), test_array_4.data(), + test_array_2.size()); + } + t3 = get_time(); + ccprintf(" %" PRId64 " us) ", t3.val - t2.val); + + return EC_SUCCESS; +} + +extern "C" void run_test(int, const char **) +{ + test_reset(); + RUN_TEST(test_unaligned_access); + RUN_TEST(benchmark_unaligned_access_memcpy); + RUN_TEST(benchmark_unaligned_access_array); + test_print_result(); +} diff --git a/test/unaligned_access.tasklist b/test/unaligned_access.tasklist new file mode 100644 index 0000000000..2d177cee59 --- /dev/null +++ b/test/unaligned_access.tasklist @@ -0,0 +1,9 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST \ No newline at end of file -- cgit v1.2.1 From f21e3bc823547c9cac5b36ba2f8358ab806b7ce3 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Tue, 9 May 2023 13:18:51 +0000 Subject: doc: zephyr_troubleshooting: add a note about macro expansion Add a note about the new config option CONFIG_COMPILER_TRACK_MACRO_EXPANSION, and also add an example on how to disable LTO without changing the project file itself. BUG=none TEST=check the page on gitiles Change-Id: I3af8b5ba4f8a0e59a419e426baa4d5460040e86c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4516858 Commit-Queue: Fabio Baltieri Tested-by: Fabio Baltieri Reviewed-by: Keith Short --- docs/zephyr/zephyr_troubleshooting.md | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/docs/zephyr/zephyr_troubleshooting.md b/docs/zephyr/zephyr_troubleshooting.md index aa6980a9d5..3f3cc508cc 100644 --- a/docs/zephyr/zephyr_troubleshooting.md +++ b/docs/zephyr/zephyr_troubleshooting.md @@ -135,13 +135,23 @@ example a missing `struct device` can show as /tmp/ccCiGy7c.ltrans0.ltrans.o:(.rodata+0x6a0): undefined reference to `__device_dts_ord_75' ``` -Adding `CONFIG_LTO=n` to the corresponding `prj.conf` usually results in more -useful error messages, for example: +Adding `CONFIG_LTO=n` to the corresponding `prj.conf` or building with `zmake +build -DCONFIG_LTO=n` usually results in more useful error messages, +for example: ``` modules/ec/libec_shim.a(adc.c.obj):(.rodata.adc_channels+0x58): undefined reference to `__device_dts_ord_75' ``` +## Macro Error Expansion + +GCC errors on macros include macro expansion by default. This usually results +in a wall of errors that makes it very hard to identify the actual problem. For +these situations it's useful to disable macro expansion entirely by setting +`CONFIG_COMPILER_TRACK_MACRO_EXPANSION=n`, for example by building with: + +`zmake build -DCONFIG_COMPILER_TRACK_MACRO_EXPANSION=n` + ## Build artifacts The buildsystem can be configured to leave the build artifact next to the -- cgit v1.2.1 From 5cc8ef46cfbca7aeff4023df27ebd4af02ea81d2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 8 May 2023 15:52:14 -0600 Subject: charger: Delete charge_state_v2.h This is not used any more. Delete it. This makes no functional change. BUG=b:218332694 TEST=make buildall Change-Id: I982d9ac1e593232518850ad061480cd9746cfcbe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4516192 Tested-by: Simon Glass Reviewed-by: Abe Levkoy Reviewed-by: Paul Fagerburg Commit-Queue: Eric Peers --- include/charge_state_v2.h | 9 --------- 1 file changed, 9 deletions(-) delete mode 100644 include/charge_state_v2.h diff --git a/include/charge_state_v2.h b/include/charge_state_v2.h deleted file mode 100644 index 72fd8a88ff..0000000000 --- a/include/charge_state_v2.h +++ /dev/null @@ -1,9 +0,0 @@ -/* Copyright 2014 The ChromiumOS Authors - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_CHARGE_STATE_V2_H -#define __CROS_EC_CHARGE_STATE_V2_H - -#endif /* __CROS_EC_CHARGE_STATE_V2_H */ -- cgit v1.2.1 From 8d1ea27042db3f86cdf05fea26423864caf04d4b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 8 May 2023 16:12:47 -0600 Subject: charger: Rename enum charge_state_v2 to charge_state Now that we don't have an old charge_state, this is the only one. Rename it accordingly. This makes no functional change. BUG=b:218332694 TEST=make buildall Change-Id: I95923eedd2715b8c7793df8f6e3171c82f9347ca Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4516193 Reviewed-by: Tristan Honscheid Tested-by: Simon Glass Commit-Queue: Eric Peers --- common/charge_state_v2.c | 6 +++--- include/charge_state.h | 6 +++--- test/sbs_charging_v2.c | 16 ++++++++-------- .../drivers/common_charger/src/test_charge_state_v2.c | 18 +++++++++--------- 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/common/charge_state_v2.c b/common/charge_state_v2.c index a603d4f108..abfb6d2dd0 100644 --- a/common/charge_state_v2.c +++ b/common/charge_state_v2.c @@ -80,7 +80,7 @@ static uint8_t battery_level_shutdown; */ static const struct battery_info *batt_info; static struct charge_state_data curr; -static enum charge_state_v2 prev_state; +static enum charge_state prev_state; static int prev_ac, prev_charge, prev_disp_charge; static enum battery_present prev_bp; static enum ec_charge_control_mode chg_ctl_mode; @@ -776,7 +776,7 @@ static void notify_host_of_low_battery_charge(void) #endif } -static void set_charge_state(enum charge_state_v2 state) +static void set_charge_state(enum charge_state state) { prev_state = curr.state; curr.state = state; @@ -1026,7 +1026,7 @@ static void wakeup_battery(int *need_static) } } -__test_only enum charge_state_v2 charge_get_state_v2(void) +__test_only enum charge_state charge_get_state(void) { return curr.state; } diff --git a/include/charge_state.h b/include/charge_state.h index 34576dc333..ed7ca0a4d9 100644 --- a/include/charge_state.h +++ b/include/charge_state.h @@ -83,7 +83,7 @@ enum led_pwr_state { * only to control the LEDs (with one not-quite-correct exception). For V2 * we use a different set of states internally. */ -enum charge_state_v2 { +enum charge_state { ST_IDLE = 0, ST_DISCHARGE, ST_CHARGE, @@ -98,7 +98,7 @@ struct charge_state_data { int batt_is_charging; struct charger_params chg; struct batt_params batt; - enum charge_state_v2 state; + enum charge_state state; int requested_voltage; int requested_current; int desired_input_current; @@ -126,7 +126,7 @@ enum led_pwr_state led_pwr_get_state(void); /** * Return current charge v2 state. */ -__test_only enum charge_state_v2 charge_get_state_v2(void); +__test_only enum charge_state charge_get_state(void); /** * Return non-zero if battery is so low we want to keep AP off. diff --git a/test/sbs_charging_v2.c b/test/sbs_charging_v2.c index 482770ff1c..7c20bbe4ac 100644 --- a/test/sbs_charging_v2.c +++ b/test/sbs_charging_v2.c @@ -2,7 +2,7 @@ * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * - * Test charge_state_v2 behavior + * Test charge_state behavior */ #include "battery_smart.h" @@ -367,7 +367,7 @@ test_static int test_low_battery(void) test_static int test_deep_charge_battery(void) { - enum charge_state_v2 state_v2; + enum charge_state state; const struct battery_info *bat_info = battery_get_info(); test_setup(1); @@ -375,22 +375,22 @@ test_static int test_deep_charge_battery(void) /* battery pack voltage bellow voltage_min */ sb_write(SB_VOLTAGE, (bat_info->voltage_min - 200)); wait_charging_state(); - state_v2 = charge_get_state_v2(); - TEST_ASSERT(state_v2 == ST_PRECHARGE); + state = charge_get_state(); + TEST_ASSERT(state == ST_PRECHARGE); /* * Battery voltage keep bellow voltage_min, * precharge over time CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT */ usleep(CONFIG_BATTERY_LOW_VOLTAGE_TIMEOUT); - state_v2 = charge_get_state_v2(); - TEST_ASSERT(state_v2 == ST_IDLE); + state = charge_get_state(); + TEST_ASSERT(state == ST_IDLE); /* recovery from a low voltage. */ sb_write(SB_VOLTAGE, (bat_info->voltage_normal)); wait_charging_state(); - state_v2 = charge_get_state_v2(); - TEST_ASSERT(state_v2 == ST_CHARGE); + state = charge_get_state(); + TEST_ASSERT(state == ST_CHARGE); return EC_SUCCESS; } diff --git a/zephyr/test/drivers/common_charger/src/test_charge_state_v2.c b/zephyr/test/drivers/common_charger/src/test_charge_state_v2.c index a62ec2b0ea..b900e97661 100644 --- a/zephyr/test/drivers/common_charger/src/test_charge_state_v2.c +++ b/zephyr/test/drivers/common_charger/src/test_charge_state_v2.c @@ -12,35 +12,35 @@ int battery_outside_charging_temperature(void); -struct charge_state_v2_fixture { +struct charge_state_fixture { struct charge_state_data charge_state_data; }; static void *setup(void) { - static struct charge_state_v2_fixture fixture; + static struct charge_state_fixture fixture; return &fixture; } static void before(void *f) { - struct charge_state_v2_fixture *fixture = f; + struct charge_state_fixture *fixture = f; fixture->charge_state_data = *charge_get_status(); } static void after(void *f) { - struct charge_state_v2_fixture *fixture = f; + struct charge_state_fixture *fixture = f; *charge_get_status() = fixture->charge_state_data; } -ZTEST_SUITE(charge_state_v2, drivers_predicate_post_main, setup, before, after, +ZTEST_SUITE(charge_state, drivers_predicate_post_main, setup, before, after, NULL); -ZTEST(charge_state_v2, test_battery_flag_bad_temperature) +ZTEST(charge_state, test_battery_flag_bad_temperature) { struct charge_state_data *curr = charge_get_status(); @@ -48,7 +48,7 @@ ZTEST(charge_state_v2, test_battery_flag_bad_temperature) zassert_ok(battery_outside_charging_temperature()); } -ZTEST(charge_state_v2, test_battery_temperature_range) +ZTEST(charge_state, test_battery_temperature_range) { struct charge_state_data *curr = charge_get_status(); const struct battery_info *batt_info = battery_get_info(); @@ -98,7 +98,7 @@ ZTEST(charge_state_v2, test_battery_temperature_range) zassert_ok(battery_outside_charging_temperature()); } -ZTEST(charge_state_v2, test_current_limit_derating) +ZTEST(charge_state, test_current_limit_derating) { int charger_current_limit; @@ -115,7 +115,7 @@ ZTEST(charge_state_v2, test_current_limit_derating) charger_current_limit); } -ZTEST(charge_state_v2, test_minimum_current_limit) +ZTEST(charge_state, test_minimum_current_limit) { int charger_current_limit; -- cgit v1.2.1 From bfaf5b4b479fd3b4ef713d6e9e85392dc2652467 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Thu, 11 May 2023 19:40:20 -0700 Subject: ppc: ktu1125: Fix register used for VCONN control The register that was being used to enable/disable VCONN (KTU1125_SET_SW_CFG) was incorrect. It should be KTU1125_CTRL_SW_CFG. In addition, VCONN was being applied to wrong CC line. KTU1125_CC1S_VCONN --> applies VCONN to CC1 when the polarity is CC2 KTU1125_CC2S_VCONN --> applies VCONN to CC2 when the polarity is CC1 BUG=b:267589112 TEST=Verfied using totalphase that VCONN is being enabled and the CC voltage of the CC data line is correct. Change-Id: I45c85800849dbabeac36d976525de7d058ad23f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4519354 Tested-by: Scott Collyer Reviewed-by: Diana Z Reviewed-by: Boris Mittelberg Commit-Queue: Scott Collyer --- driver/ppc/ktu1125.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/driver/ppc/ktu1125.c b/driver/ppc/ktu1125.c index 647512d801..24b03e8538 100644 --- a/driver/ppc/ktu1125.c +++ b/driver/ppc/ktu1125.c @@ -348,11 +348,15 @@ static int ktu1125_set_vconn(int port, int enable) polarity = polarity_rm_dts(pd_get_polarity(port)); if (enable) { - flags |= polarity ? KTU1125_CC2S_VCONN : KTU1125_CC1S_VCONN; - status = set_flags(port, KTU1125_SET_SW_CFG, flags); + /* + * If polarity is CC1, then apply VCONN on CC2. + * else if polarity is CC2, then apply VCONN on CC1 + */ + flags |= polarity ? KTU1125_CC1S_VCONN : KTU1125_CC2S_VCONN; + status = set_flags(port, KTU1125_CTRL_SW_CFG, flags); } else { flags |= KTU1125_CC1S_VCONN | KTU1125_CC2S_VCONN; - status = clr_flags(port, KTU1125_SET_SW_CFG, flags); + status = clr_flags(port, KTU1125_CTRL_SW_CFG, flags); } return status; -- cgit v1.2.1 From 7b963a79c884a1584120e5413eae489679a30183 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Mon, 15 May 2023 17:30:22 +0000 Subject: ec: Add #line in include/system.h Work around coreboot GCC preprocessor bug. BUG=b:272518464 TEST=gcc -E Change-Id: I609d019680bedddc8deea0f377c8bee4df6f5df1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4533365 Commit-Queue: Aaron Massey Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis Reviewed-by: Aaron Massey --- include/system.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/system.h b/include/system.h index c7884199e1..064656fd5f 100644 --- a/include/system.h +++ b/include/system.h @@ -5,6 +5,12 @@ /* System module for Chrome EC */ +/* + * TODO(b/272518464): Work around coreboot GCC preprocessor bug. + * #line marks the *next* line, so it is off by one. + */ +#line 13 + #ifndef __CROS_EC_SYSTEM_H #define __CROS_EC_SYSTEM_H -- cgit v1.2.1 From 42167827fbbc9d0100f151c2980d15a46e61957b Mon Sep 17 00:00:00 2001 From: Rob Barnes Date: Thu, 20 Apr 2023 10:28:28 -0600 Subject: tasks: Only report stack overflow if task is enabled Don't report stack overflow on a task that has been disabled. Without this change, system safe mode will fail to recover from a stackoverflow because the stackoverflow will be detected again, even though the task has already been disabled. BUG=b:278792557 TEST=System safe mode starts on boten after a stackoverflow Change-Id: I59ab579c296d108dcd8c5aba9cb32bba6c7bbf54 Signed-off-by: Rob Barnes Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4455298 Reviewed-by: Daisuke Nojiri Reviewed-by: Boris Mittelberg --- core/cortex-m/task.c | 3 ++- core/cortex-m0/task.c | 3 ++- core/minute-ia/task.c | 3 ++- core/nds32/task.c | 8 +++++--- core/riscv-rv32i/task.c | 8 +++++--- 5 files changed, 16 insertions(+), 9 deletions(-) diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 336cafc99a..f42b4f9dc0 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -301,7 +301,8 @@ void svc_handler(int desched, task_id_t resched) current = current_task; #ifdef CONFIG_DEBUG_STACK_OVERFLOW - if (*current->stack != STACK_UNUSED_VALUE) { + if (*current->stack != STACK_UNUSED_VALUE && + task_enabled(current - tasks)) { panic_printf("\n\nStack overflow in %s task!\n", task_names[current - tasks]); software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks); diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c index f63e9824db..315b8d6d16 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c @@ -231,7 +231,8 @@ task_ __attribute__((noinline)) * __svc_handler(int desched, task_id_t resched) current = current_task; #ifdef CONFIG_DEBUG_STACK_OVERFLOW - if (*current->stack != STACK_UNUSED_VALUE) { + if (*current->stack != STACK_UNUSED_VALUE && + task_enabled(current - tasks)) { panic_printf("\n\nStack overflow in %s task!\n", task_names[current - tasks]); software_panic(PANIC_SW_STACK_OVERFLOW, current - tasks); diff --git a/core/minute-ia/task.c b/core/minute-ia/task.c index 3e072344df..6322125247 100644 --- a/core/minute-ia/task.c +++ b/core/minute-ia/task.c @@ -221,7 +221,8 @@ uint32_t switch_handler(int desched, task_id_t resched) current = current_task; if (IS_ENABLED(CONFIG_DEBUG_STACK_OVERFLOW) && - *current->stack != STACK_UNUSED_VALUE) { + *current->stack != STACK_UNUSED_VALUE && + task_enabled(current - tasks)) { panic_printf("\n\nStack overflow in %s task!\n", task_get_name(current - tasks)); diff --git a/core/nds32/task.c b/core/nds32/task.c index 201c8731fc..bbfc5f79c7 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -309,9 +309,11 @@ task_ *next_sched_task(void) #ifdef CONFIG_DEBUG_STACK_OVERFLOW if (*current_task->stack != STACK_UNUSED_VALUE) { int i = task_get_current(); - - panic_printf("\n\nStack overflow in %s task!\n", task_names[i]); - software_panic(PANIC_SW_STACK_OVERFLOW, i); + if (task_enabled(i)) { + panic_printf("\n\nStack overflow in %s task!\n", + task_names[i]); + software_panic(PANIC_SW_STACK_OVERFLOW, i); + } } #endif diff --git a/core/riscv-rv32i/task.c b/core/riscv-rv32i/task.c index 977987277b..48244bc1b2 100644 --- a/core/riscv-rv32i/task.c +++ b/core/riscv-rv32i/task.c @@ -289,9 +289,11 @@ task_ *__ram_code next_sched_task(void) #ifdef CONFIG_DEBUG_STACK_OVERFLOW if (*current_task->stack != STACK_UNUSED_VALUE) { int i = task_get_current(); - - panic_printf("\n\nStack overflow in %s task!\n", task_names[i]); - software_panic(PANIC_SW_STACK_OVERFLOW, i); + if (task_enabled(i)) { + panic_printf("\n\nStack overflow in %s task!\n", + task_names[i]); + software_panic(PANIC_SW_STACK_OVERFLOW, i); + } } #endif -- cgit v1.2.1 From 322687ee44e3a4d5fec5cdf0c240c655e1b7f47c Mon Sep 17 00:00:00 2001 From: David Cross Date: Thu, 4 May 2023 14:29:02 -0700 Subject: chip: add support for npcx trng BUG=b:280889889 TEST=add CONFIG_RNG to NPCX based board.h file (e.g. npcx9_evb) Change-Id: I93b3a7742c3b7d614cc1218104cd642b3339f8b3 Signed-off-by: David Cross Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4507895 Reviewed-by: Bobby Casey --- chip/npcx/build.mk | 1 + chip/npcx/trng.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 chip/npcx/trng.c diff --git a/chip/npcx/build.mk b/chip/npcx/build.mk index 9e046be7ec..11155af9bb 100644 --- a/chip/npcx/build.mk +++ b/chip/npcx/build.mk @@ -40,6 +40,7 @@ chip-$(CONFIG_CEC)+=cec.o # pwm functions are implemented with the fan functions chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_SPI)+=spi.o +chip-$(CONFIG_RNG)+=trng.o chip-$(CONFIG_WATCHDOG)+=watchdog.o ifndef CONFIG_KEYBOARD_DISCRETE chip-$(HAS_TASK_KEYSCAN)+=keyboard_raw.o diff --git a/chip/npcx/trng.c b/chip/npcx/trng.c new file mode 100644 index 0000000000..a2d7920c14 --- /dev/null +++ b/chip/npcx/trng.c @@ -0,0 +1,251 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Hardware Random Number Generator */ + +#include "common.h" +#include "console.h" +#include "host_command.h" +#include "panic.h" +#include "printf.h" +#include "registers.h" +#include "system.h" +#include "task.h" +#include "trng.h" +#include "util.h" + +#define DRBG_CONTEXT_SIZE 240 + +struct drbg_ctx { + union { + uint8_t buffer[DRBG_CONTEXT_SIZE]; + uint32_t buffer32[DRBG_CONTEXT_SIZE / 4]; + uint64_t buffer64[DRBG_CONTEXT_SIZE / 8]; + }; +} __aligned(16); + +struct drbg_ctx ctx; +struct drbg_ctx *ctx_p = &ctx; + +enum ncl_status { + NCL_STATUS_OK = 0xA5A5, + NCL_STATUS_FAIL = 0x5A5A, + NCL_STATUS_INVALID_PARAM = 0x02, + NCL_STATUS_PARAM_NOT_SUPPORTED, + NCL_STATUS_SYSTEM_BUSY, + NCL_STATUS_AUTHENTICATION_FAIL, + NCL_STATUS_NO_RESPONSE, + NCL_STATUS_HARDWARE_ERROR, +}; + +/* + * This enum defines the security strengths supported by this DRBG mechanism. + * The internally generated entropy and nonce sizes are derived from these + * values. The supported actual sizes: + * Security strength (bits) 112 128 192 256 128_Test 256_Test + * + * Entropy size (Bytes) 32 48 64 96 111 128 + * Nonce size (Bytes) 16 16 24 32 16 0 + */ +enum ncl_drbg_security_strength { + NCL_DRBG_SECURITY_STRENGTH_112b = 0, + NCL_DRBG_SECURITY_STRENGTH_128b, + NCL_DRBG_SECURITY_STRENGTH_192b, + NCL_DRBG_SECURITY_STRENGTH_256b, + NCL_DRBG_SECURITY_STRENGTH_128b_TEST, + NCL_DRBG_SECURITY_STRENGTH_256b_TEST, + NCL_DRBG_MAX_SECURITY_STRENGTH +}; + +/* The actual base address is 13C but we only need the SHA power function */ +#define NCL_SHA_BASE_ADDR 0x0000015CUL +struct ncl_sha { + /* Power on/off SHA module. */ + enum ncl_status (*power)(void *ctx, uint8_t on); +}; +#define NCL_SHA ((const struct ncl_sha *)NCL_SHA_BASE_ADDR) + +/* + * The base address of the table that holds the function pointer for each + * DRBG API in ROM. + */ +#define NCL_DRBG_BASE_ADDR 0x00000110UL +struct ncl_drbg { + /* Get the DRBG context size required by DRBG APIs. */ + uint32_t (*get_context_size)(void); + /* Initialize DRBG context. */ + enum ncl_status (*init_context)(void *ctx); + /* Power on/off DRBG module. */ + enum ncl_status (*power)(void *ctx, uint8_t on); + /* Finalize DRBG context. */ + enum ncl_status (*finalize_context)(void *ctx); + /* Initialize the DRBG hardware module and enable interrupts. */ + enum ncl_status (*init)(void *ctx, bool int_enable); + /* + * Configure DRBG, pres_resistance enables/disables (1/0) prediction + * resistance + */ + enum ncl_status (*config)(void *ctx, uint32_t reseed_interval, + uint8_t pred_resistance); + /* + * This routine creates a first instantiation of the DRBG mechanism + * parameters. The routine pulls an initial seed from the HW RNG module + * and resets the reseed counter. DRBG and SHA modules should be + * activated prior to the this operation. + */ + enum ncl_status (*instantiate)( + void *ctx, enum ncl_drbg_security_strength sec_strength, + const uint8_t *pers_string, uint32_t pers_string_len); + /* Uninstantiate DRBG module */ + enum ncl_status (*uninstantiate)(void *ctx); + /* Reseeds the internal state of the given instantce */ + enum ncl_status (*reseed)(void *ctc, uint8_t *add_data, + uint32_t add_data_len); + /* Generates a random number from the current internal state. */ + enum ncl_status (*generate)(void *ctx, const uint8_t *add_data, + uint32_t add_data_len, uint8_t *out_buff, + uint32_t out_buff_len); + /* Clear all DRBG SSPs (Sensitive Security Parameters) in HW & driver */ + enum ncl_status (*clear)(void *ctx); +}; +#define NCL_DRBG ((const struct ncl_drbg *)NCL_DRBG_BASE_ADDR) + +struct npcx_trng_state { + enum ncl_status trng_init; +}; +struct npcx_trng_state trng_state; +struct npcx_trng_state *state_p = &trng_state; + +test_mockable void trng_init(void) +{ +#ifndef CHIP_VARIANT_NPCX9M8S +#error "Please add support for CONFIG_RNG on this chip family." +#endif + + uint32_t context_size = 0; + + state_p->trng_init = NCL_STATUS_FAIL; + + context_size = NCL_DRBG->get_context_size(); + if (context_size != DRBG_CONTEXT_SIZE) + ccprintf("ERROR! Unexpected NCL DRBG context_size = %d\n", + context_size); + + state_p->trng_init = NCL_DRBG->power(ctx_p, true); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG power returned %x\n", state_p->trng_init); + return; + } + + state_p->trng_init = NCL_SHA->power(ctx_p, true); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! SHA power returned %x\n", state_p->trng_init); + return; + } + + state_p->trng_init = NCL_DRBG->init_context(ctx_p); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG init_context returned %x\r", + state_p->trng_init); + return; + } + + state_p->trng_init = NCL_DRBG->init(ctx_p, 0); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG init returned %x\r", state_p->trng_init); + return; + } + + state_p->trng_init = NCL_DRBG->config(ctx_p, 100, false); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG config returned %x\r", + state_p->trng_init); + return; + } + + state_p->trng_init = NCL_DRBG->instantiate( + ctx_p, NCL_DRBG_SECURITY_STRENGTH_128b, NULL, 0); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG instantiate returned %x\r", + state_p->trng_init); + return; + } + + state_p->trng_init = NCL_DRBG->power(ctx_p, false); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG power returned %x\n", state_p->trng_init); + return; + } + + state_p->trng_init = NCL_SHA->power(ctx_p, false); + if (state_p->trng_init != NCL_STATUS_OK) { + ccprintf("ERROR! SHA power returned %x\n", state_p->trng_init); + return; + } +} + +uint32_t trng_rand(void) +{ + uint32_t return_value; + enum ncl_status status = NCL_STATUS_FAIL; + + /* Don't attempt generate and panic if initialization failed */ + if (state_p->trng_init != NCL_STATUS_OK) + software_panic(PANIC_SW_BAD_RNG, task_get_current()); + + status = NCL_DRBG->power(ctx_p, true); + if (status != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG power returned %x\n", status); + software_panic(PANIC_SW_BAD_RNG, task_get_current()); + } + + status = NCL_SHA->power(ctx_p, true); + if (status != NCL_STATUS_OK) { + ccprintf("ERROR! SHA power returned %x\n", status); + software_panic(PANIC_SW_BAD_RNG, task_get_current()); + } + + status = NCL_DRBG->generate(NULL, NULL, 0, (uint8_t *)&return_value, 4); + if (status != NCL_STATUS_OK) { + ccprintf("ERROR! DRBG generate returned %x\r", status); + software_panic(PANIC_SW_BAD_RNG, task_get_current()); + } + + /* + * Failing to turn off the blocks has power implications but wouldn't + * result in feeding the caller a bad result, hence no panics enabled + * for failing to turn off the hardware + */ + status = NCL_DRBG->power(ctx_p, false); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! DRBG power returned %x\n", status); + + status = NCL_SHA->power(ctx_p, false); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! SHA power returned %x\n", status); + + return return_value; +} + +test_mockable void trng_exit(void) +{ + enum ncl_status status = NCL_STATUS_FAIL; + + status = NCL_DRBG->clear(ctx_p); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! DRBG clear returned %x\r", status); + + status = NCL_DRBG->uninstantiate(ctx_p); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! DRBG uninstantiate returned %x\r", status); + + status = NCL_DRBG->power(ctx_p, false); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! DRBG power returned %x\n", status); + + status = NCL_SHA->power(ctx_p, false); + if (status != NCL_STATUS_OK) + ccprintf("ERROR! SHA power returned %x\n", status); +} -- cgit v1.2.1 From 9b983d87013e63d4c0de79a0ca9b95725f1200eb Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 10 May 2023 10:11:16 -0700 Subject: NPCX9: Allow boards to customize MIWU interrupt priority This CL will add macros used to set MIWU interrupt priorities. These macro can be set by each board to adjust priorities as needed. BUG=b:279918234 TEST=build agah Change-Id: Ide840e4ab8cc9aa8deb83b6ad76fa64bc0d83972 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4518230 Auto-Submit: Daisuke Nojiri Reviewed-by: Tarun Tuli Tested-by: Daisuke Nojiri Reviewed-by: Mulin Chao Commit-Queue: Daisuke Nojiri --- chip/npcx/gpio-npcx9.c | 33 +++++++++++++++++---------------- chip/npcx/registers.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 16 deletions(-) diff --git a/chip/npcx/gpio-npcx9.c b/chip/npcx/gpio-npcx9.c index 5de8ea3b0a..3a7378083c 100644 --- a/chip/npcx/gpio-npcx9.c +++ b/chip/npcx/gpio-npcx9.c @@ -181,21 +181,22 @@ GPIO_IRQ_FUNC(__gpio_wk1e_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_5)); GPIO_IRQ_FUNC(__gpio_wk1f_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_6)); GPIO_IRQ_FUNC(__gpio_wk1g_interrupt, WUI_INT(MIWU_TABLE_1, MIWU_GROUP_7)); -DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_CR_SIN2_WKINTA_0, __gpio_cr_sin2_interrupt, + NPCX_MIWU0_GROUP_A); +DECLARE_IRQ(NPCX_IRQ_TWD_WKINTB_0, __gpio_wk0b_interrupt, NPCX_MIWU0_GROUP_B); +DECLARE_IRQ(NPCX_IRQ_WKINTC_0, __gpio_wk0c_interrupt, NPCX_MIWU0_GROUP_C); +DECLARE_IRQ(NPCX_IRQ_MTC_WKINTD_0, __gpio_rtc_interrupt, NPCX_MIWU0_GROUP_D); +DECLARE_IRQ(NPCX_IRQ_WKINTE_0, __gpio_host_interrupt, NPCX_MIWU0_GROUP_E); +DECLARE_IRQ(NPCX_IRQ_WKINTF_0, __gpio_wk0f_interrupt, NPCX_MIWU0_GROUP_F); +DECLARE_IRQ(NPCX_IRQ_WKINTG_0, __gpio_wk0g_interrupt, NPCX_MIWU0_GROUP_G); +DECLARE_IRQ(NPCX_IRQ_WKINTH_0, __gpio_wk0h_interrupt, NPCX_MIWU0_GROUP_H); +DECLARE_IRQ(NPCX_IRQ_WKINTA_1, __gpio_wk1a_interrupt, NPCX_MIWU1_GROUP_A); +DECLARE_IRQ(NPCX_IRQ_WKINTB_1, __gpio_wk1b_interrupt, NPCX_MIWU1_GROUP_B); #ifdef NPCX_SELECT_KSI_TO_GPIO -DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, __gpio_wk1c_interrupt, NPCX_MIWU1_GROUP_C); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTD_1, __gpio_wk1d_interrupt, NPCX_MIWU1_GROUP_D); +DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, NPCX_MIWU1_GROUP_E); #ifdef CONFIG_HOST_INTERFACE_SHI /* * HACK: Make CS GPIO P2 to improve SHI reliability. @@ -204,10 +205,10 @@ DECLARE_IRQ(NPCX_IRQ_WKINTE_1, __gpio_wk1e_interrupt, 3); */ DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 2); #else -DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTF_1, __gpio_wk1f_interrupt, NPCX_MIWU1_GROUP_F); #endif -DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, 3); -DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, 3); +DECLARE_IRQ(NPCX_IRQ_WKINTG_1, __gpio_wk1g_interrupt, NPCX_MIWU1_GROUP_G); +DECLARE_IRQ(NPCX_IRQ_WKINTH_1, __gpio_wk1h_interrupt, NPCX_MIWU1_GROUP_H); DECLARE_IRQ(NPCX_IRQ_LCT_WKINTF_2, __gpio_lct_interrupt, 3); #undef GPIO_IRQ_FUNC diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index a583fb1c64..c99fb76bf3 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -275,6 +275,56 @@ enum { MIWU_EDGE_ANYING, }; +#define NPCX_MIWU_DEFAULT_PRIORITY 3 +#ifndef NPCX_MIWU0_GROUP_A +#define NPCX_MIWU0_GROUP_A NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_B +#define NPCX_MIWU0_GROUP_B NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_C +#define NPCX_MIWU0_GROUP_C NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_D +#define NPCX_MIWU0_GROUP_D NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_E +#define NPCX_MIWU0_GROUP_E NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_F +#define NPCX_MIWU0_GROUP_F NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_G +#define NPCX_MIWU0_GROUP_G NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU0_GROUP_H +#define NPCX_MIWU0_GROUP_H NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_A +#define NPCX_MIWU1_GROUP_A NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_B +#define NPCX_MIWU1_GROUP_B NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_C +#define NPCX_MIWU1_GROUP_C NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_D +#define NPCX_MIWU1_GROUP_D NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_E +#define NPCX_MIWU1_GROUP_E NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_F +#define NPCX_MIWU1_GROUP_F NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_G +#define NPCX_MIWU1_GROUP_G NPCX_MIWU_DEFAULT_PRIORITY +#endif +#ifndef NPCX_MIWU1_GROUP_H +#define NPCX_MIWU1_GROUP_H NPCX_MIWU_DEFAULT_PRIORITY +#endif + /* MIWU utilities */ #define MIWU_TABLE_WKKEY MIWU_TABLE_1 #define MIWU_GROUP_WKKEY MIWU_GROUP_3 -- cgit v1.2.1 From 66e1205cb6cae3ca3c6223fdbd91c7cbedf127d7 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 10 May 2023 10:11:16 -0700 Subject: Agah: Give SEQ_EC_DSW_PWROK interrupt higher priority This CL gives SEQ_EC_DSW_PWROK interrupt a higher priority to reduce the latency of PCH_PWROK. BUG=b:279918234 TEST=Agah. Latency is reduced to 18 usec. Change-Id: I0cca3e6d5c7bc97eefddc0958eaeb0b65007e5fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4518231 Auto-Submit: Daisuke Nojiri Commit-Queue: Daisuke Nojiri Reviewed-by: Tarun Tuli Tested-by: Daisuke Nojiri --- board/agah/board.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/agah/board.h b/board/agah/board.h index ba2889130d..b0a6077f6d 100644 --- a/board/agah/board.h +++ b/board/agah/board.h @@ -155,6 +155,9 @@ #define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG +/* Give SEQ_EC_DSW_PWROK higher priority to reduce latency for PCH_PWROK. */ +#define NPCX_MIWU0_GROUP_F 1 + #ifndef __ASSEMBLER__ #include "gpio_signal.h" /* needed by registers.h */ -- cgit v1.2.1 From 69f476737a9167bd5d650d74d2f2e809ef203275 Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 10 May 2023 10:11:16 -0700 Subject: Hades: Give SEQ_EC_DSW_PWROK interrupt higher priority This CL gives SEQ_EC_DSW_PWROK interrupt a higher priority to reduce the latency of PCH_PWROK. BUG=b:279918234 TEST=Agah. Latency is reduced to 18 usec. Change-Id: I359b045a7078862bd0d32fa0121c93dee3ef9f7e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4520132 Commit-Queue: Daisuke Nojiri Reviewed-by: Tarun Tuli Auto-Submit: Daisuke Nojiri Tested-by: Daisuke Nojiri --- board/hades/board.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/hades/board.h b/board/hades/board.h index 31baee2038..86f24eb47c 100644 --- a/board/hades/board.h +++ b/board/hades/board.h @@ -160,6 +160,9 @@ #define CONFIG_ADC_CHANNELS_RUNTIME_CONFIG +/* Give SEQ_EC_DSW_PWROK IRQ higher priority to reduce latency for PCH_PWROK. */ +#define NPCX_MIWU0_GROUP_F 1 + #ifndef __ASSEMBLER__ #include "gpio_signal.h" /* needed by registers.h */ -- cgit v1.2.1 From efe0fbc416966340abae6539df8b2ab5a7e5a219 Mon Sep 17 00:00:00 2001 From: lschyi Date: Mon, 15 May 2023 15:37:12 +0800 Subject: corsola: Fix reported USB-C ports for no DB design with DB detection on The definition of `CORSOLA_DB_NONE` was settled to no DB in the project in the previous CL "corsola: Update implementation for no daughter board ", and the USB-C counts is determined by dts settings in previous CL " corosla: Improve USB-C port configuration". This introduces a reported port number mismatch when the DB detection is enabled, and the desired detection result is no DB in the design. Extend the DB status enum with `CORSOLA_DB_NO_DETECTION` to properly describe the different DB status, and fix the reported USB-C port logic. BUG=b:282625153 TEST=`zmake build --clobber` Change-Id: Idd55381759677272e0bfc7b270647d759642ce01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4530326 Reviewed-by: Ting Shen Tested-by: Sung-Chi Li Commit-Queue: Sung-Chi Li --- .../program/corsola/include/variant_db_detection.h | 5 +- zephyr/program/corsola/src/usbc.c | 6 +- zephyr/test/kingler/CMakeLists.txt | 6 ++ zephyr/test/kingler/Kconfig | 6 ++ zephyr/test/kingler/src/fakes.c | 5 +- zephyr/test/kingler/src/usb_port_count.c | 90 ++++++++++++++++++++++ zephyr/test/kingler/testcase.yaml | 5 ++ 7 files changed, 119 insertions(+), 4 deletions(-) create mode 100644 zephyr/test/kingler/src/usb_port_count.c diff --git a/zephyr/program/corsola/include/variant_db_detection.h b/zephyr/program/corsola/include/variant_db_detection.h index cf86e1ae1c..fb468126ef 100644 --- a/zephyr/program/corsola/include/variant_db_detection.h +++ b/zephyr/program/corsola/include/variant_db_detection.h @@ -12,6 +12,9 @@ enum corsola_db_type { CORSOLA_DB_UNINIT = -1, + /* CORSOLA_DB_NO_DETECTION means there is no detection involved in. */ + CORSOLA_DB_NO_DETECTION, + /* CORSOLA_DB_NONE means there is no DB in the design. */ CORSOLA_DB_NONE, CORSOLA_DB_TYPEC, CORSOLA_DB_HDMI, @@ -28,7 +31,7 @@ enum corsola_db_type corsola_get_db_type(void); #elif !defined(CONFIG_TEST) inline enum corsola_db_type corsola_get_db_type(void) { - return CORSOLA_DB_NONE; + return CORSOLA_DB_NO_DETECTION; } #endif diff --git a/zephyr/program/corsola/src/usbc.c b/zephyr/program/corsola/src/usbc.c index 71c02ff54f..871c84a2e4 100644 --- a/zephyr/program/corsola/src/usbc.c +++ b/zephyr/program/corsola/src/usbc.c @@ -45,7 +45,7 @@ DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_PRE_DEFAULT); __override uint8_t board_get_usb_pd_port_count(void) { - /* This function returns the PORT_COUNT+1 when HDMI db is connected. + /* This function returns the PORT_COUNT when HDMI db is connected. * This is a trick to ensure the usb_mux_set being set properley. * HDMI display functions using the USB virtual mux to * communicate * with the DP bridge. @@ -56,6 +56,8 @@ __override uint8_t board_get_usb_pd_port_count(void) } else { return CONFIG_USB_PD_PORT_MAX_COUNT - 1; } + } else if (corsola_get_db_type() == CORSOLA_DB_NONE) { + return CONFIG_USB_PD_PORT_MAX_COUNT - 1; } return CONFIG_USB_PD_PORT_MAX_COUNT; @@ -65,7 +67,7 @@ uint8_t board_get_adjusted_usb_pd_port_count(void) { const enum corsola_db_type db = corsola_get_db_type(); - if (db == CORSOLA_DB_TYPEC || db == CORSOLA_DB_NONE) { + if (db == CORSOLA_DB_TYPEC || db == CORSOLA_DB_NO_DETECTION) { return CONFIG_USB_PD_PORT_MAX_COUNT; } else { return CONFIG_USB_PD_PORT_MAX_COUNT - 1; diff --git a/zephyr/test/kingler/CMakeLists.txt b/zephyr/test/kingler/CMakeLists.txt index f361e6eb3e..31f7b9cc2c 100644 --- a/zephyr/test/kingler/CMakeLists.txt +++ b/zephyr/test/kingler/CMakeLists.txt @@ -47,3 +47,9 @@ target_sources_ifdef(CONFIG_TEST_KINGLER_CCD app PRIVATE src/ccd.c ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/board.c) target_sources_ifdef(CONFIG_TEST_VOLTORB app PRIVATE src/voltorb_usbc.c ${PLATFORM_EC_PROGRAM_DIR}/corsola/voltorb/src/usbc.c) +target_sources_ifdef( + CONFIG_TEST_DB_DETECTION_USB_COUNT + app + PRIVATE + ${PLATFORM_EC_PROGRAM_DIR}/corsola/src/usbc.c + src/usb_port_count.c) diff --git a/zephyr/test/kingler/Kconfig b/zephyr/test/kingler/Kconfig index 4cde54ce6d..77c1f25253 100644 --- a/zephyr/test/kingler/Kconfig +++ b/zephyr/test/kingler/Kconfig @@ -71,4 +71,10 @@ config TEST_USB_PD_POLICY Include voltorb_usbc.c into the binary to test the type-c output current limit function. +config TEST_DB_DETECTION_USB_COUNT + bool "Run the tests intended for db detection" + help + Include USB-C tests into the binary for testing the reported port + count with db detection. + source "Kconfig.zephyr" diff --git a/zephyr/test/kingler/src/fakes.c b/zephyr/test/kingler/src/fakes.c index 6c67447e88..c4a7cf0a6d 100644 --- a/zephyr/test/kingler/src/fakes.c +++ b/zephyr/test/kingler/src/fakes.c @@ -14,8 +14,11 @@ FAKE_VOID_FUNC(power_signal_interrupt, enum gpio_signal); FAKE_VOID_FUNC(chipset_watchdog_interrupt, enum gpio_signal); FAKE_VOID_FUNC(extpower_interrupt, enum gpio_signal); FAKE_VOID_FUNC(switch_interrupt, enum gpio_signal); -#ifndef CONFIG_TEST_KINGLER_USBC +#if !(defined(CONFIG_TEST_KINGLER_USBC) || \ + defined(CONFIG_TEST_DB_DETECTION_USB_COUNT)) FAKE_VOID_FUNC(xhci_interrupt, enum gpio_signal); +#endif +#ifndef CONFIG_TEST_KINGLER_USBC FAKE_VOID_FUNC(lid_interrupt, enum gpio_signal); FAKE_VOID_FUNC(usb_a0_interrupt, enum gpio_signal); FAKE_VOID_FUNC(tcpc_alert_event, enum gpio_signal); diff --git a/zephyr/test/kingler/src/usb_port_count.c b/zephyr/test/kingler/src/usb_port_count.c new file mode 100644 index 0000000000..4f55bdc693 --- /dev/null +++ b/zephyr/test/kingler/src/usb_port_count.c @@ -0,0 +1,90 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "driver/tcpm/tcpm.h" +#include "ec_app_main.h" +#include "usb_charge.h" +#include "usb_pd.h" +#include "usbc_ppc.h" +#include "variant_db_detection.h" + +#include +#include +#include +#include +#include + +#define LOG_LEVEL 0 +LOG_MODULE_REGISTER(usb_port_count); + +FAKE_VALUE_FUNC(enum corsola_db_type, corsola_get_db_type); +FAKE_VALUE_FUNC(bool, in_interrupt_context); +FAKE_VOID_FUNC(bmi3xx_interrupt); +FAKE_VOID_FUNC(hdmi_hpd_interrupt); +FAKE_VOID_FUNC(ps185_hdmi_hpd_mux_set); +FAKE_VALUE_FUNC(bool, ps8743_field_update, const struct usb_mux *, uint8_t, + uint8_t, uint8_t); +FAKE_VOID_FUNC(pd_set_dual_role, int, enum pd_dual_role_states); +FAKE_VALUE_FUNC(int, tc_is_attached_src, int); + +#define FFF_FAKES_LIST(FAKE) \ + FAKE(corsola_get_db_type) \ + FAKE(in_interrupt_context) \ + FAKE(bmi3xx_interrupt) \ + FAKE(hdmi_hpd_interrupt) \ + FAKE(ps185_hdmi_hpd_mux_set) \ + FAKE(ps8743_field_update) \ + FAKE(pd_set_dual_role) \ + FAKE(tc_is_attached_src) + +struct usb_port_count_fixture { + int place_holder; +}; + +static void *usb_port_count_setup(void) +{ + static struct usb_port_count_fixture f; + + return &f; +} + +static void usb_port_count_reset_rule_before(const struct ztest_unit_test *test, + void *data) +{ + ARG_UNUSED(test); + ARG_UNUSED(data); + FFF_FAKES_LIST(RESET_FAKE); + FFF_RESET_HISTORY(); +} + +ZTEST_RULE(usb_port_count_reset_rule, usb_port_count_reset_rule_before, NULL); +ZTEST_SUITE(usb_port_count, NULL, usb_port_count_setup, NULL, NULL, NULL); + +ZTEST_F(usb_port_count, test_detect_db) +{ + struct { + enum corsola_db_type test_type; + int expected_board_get_port_count; + int expected_board_get_adjusted_port_count; + } testdata[] = { { CORSOLA_DB_UNINIT, CONFIG_USB_PD_PORT_MAX_COUNT, + CONFIG_USB_PD_PORT_MAX_COUNT - 1 }, + { CORSOLA_DB_NO_DETECTION, + CONFIG_USB_PD_PORT_MAX_COUNT, + CONFIG_USB_PD_PORT_MAX_COUNT }, + { CORSOLA_DB_NONE, CONFIG_USB_PD_PORT_MAX_COUNT - 1, + CONFIG_USB_PD_PORT_MAX_COUNT - 1 }, + { CORSOLA_DB_TYPEC, CONFIG_USB_PD_PORT_MAX_COUNT, + CONFIG_USB_PD_PORT_MAX_COUNT }, + { CORSOLA_DB_HDMI, CONFIG_USB_PD_PORT_MAX_COUNT - 1, + CONFIG_USB_PD_PORT_MAX_COUNT - 1 } }; + for (int i = 0; i < ARRAY_SIZE(testdata); i++) { + corsola_get_db_type_fake.return_val = testdata[i].test_type; + zassert_equal(board_get_usb_pd_port_count(), + testdata[i].expected_board_get_port_count); + zassert_equal( + board_get_adjusted_usb_pd_port_count(), + testdata[i].expected_board_get_adjusted_port_count); + } +} diff --git a/zephyr/test/kingler/testcase.yaml b/zephyr/test/kingler/testcase.yaml index 6bfa6f7b7e..8012c7dc4f 100644 --- a/zephyr/test/kingler/testcase.yaml +++ b/zephyr/test/kingler/testcase.yaml @@ -58,3 +58,8 @@ tests: - CONFIG_TEST_USB_PD_POLICY=y extra_dtc_overlay_files: - kingler.default.overlay + kingler.usb_port_count: + extra_configs: + - CONFIG_TEST_DB_DETECTION_USB_COUNT=y + extra_dtc_overlay_files: + - kingler.default.overlay -- cgit v1.2.1 From 638a938c277e6f214277f3ec97dfec6257fa040e Mon Sep 17 00:00:00 2001 From: Tommy Chung Date: Fri, 21 Apr 2023 20:31:14 +0800 Subject: yavilla: Add convertible related functions Yavilla has convertible sku, add convertible related functions, including motion sensors, gmr sensor, vol button. Disable motion sensors and gmr semsor for clamesell sku. BUG=b:273791621 TEST=make sure all convertible functions work. Change-Id: I29beaaae8f002c811ad1ccb8ecdd77fa78840a5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4457658 Commit-Queue: Tommy Chung Tested-by: Tommy Chung Reviewed-by: Peter Marheine Reviewed-by: Devin Lu --- zephyr/program/nissa/yavilla/gpio.dtsi | 18 ++++ zephyr/program/nissa/yavilla/motionsense.dtsi | 148 ++++++++++++++++++++++++++ zephyr/program/nissa/yavilla/overlay.dtsi | 34 ++++-- zephyr/program/nissa/yavilla/project.conf | 16 +-- zephyr/program/nissa/yavilla/project.overlay | 1 + zephyr/program/nissa/yavilla/src/board.c | 36 ++++++- 6 files changed, 234 insertions(+), 19 deletions(-) create mode 100644 zephyr/program/nissa/yavilla/motionsense.dtsi diff --git a/zephyr/program/nissa/yavilla/gpio.dtsi b/zephyr/program/nissa/yavilla/gpio.dtsi index a18e674b11..8c76048f25 100644 --- a/zephyr/program/nissa/yavilla/gpio.dtsi +++ b/zephyr/program/nissa/yavilla/gpio.dtsi @@ -34,6 +34,9 @@ named-gpios { compatible = "named-gpios"; + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; gpio_all_sys_pwrgd: all_sys_pwrgd { gpios = <&gpiob 7 GPIO_INPUT>; }; @@ -134,6 +137,9 @@ gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; enum-name = "GPIO_POWER_BUTTON_L"; }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; + }; gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { gpios = <&gpioj 4 GPIO_INPUT>; no-auto-init; @@ -178,6 +184,10 @@ gpios = <&gpiod 1 GPIO_ODR_HIGH>; no-auto-init; }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { gpios = <&gpiol 5 GPIO_OUTPUT>; enum-name = "GPIO_USB1_ILIM_SEL"; @@ -216,6 +226,14 @@ gpios = <&gpioksol 2 GPIO_OUTPUT_HIGH>; enum-name = "GPIO_KBD_KSO2"; }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; }; named-i2c-ports { diff --git a/zephyr/program/nissa/yavilla/motionsense.dtsi b/zephyr/program/nissa/yavilla/motionsense.dtsi new file mode 100644 index 0000000000..df84c36471 --- /dev/null +++ b/zephyr/program/nissa/yavilla/motionsense.dtsi @@ -0,0 +1,148 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + bma4xx-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <1 0 0 + 0 (-1) 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + 1 0 0 + 0 0 (-1)>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma4xx-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + i2c-spi-addr-flags = "BMA4_I2C_ADDR_PRIMARY"; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu &int_acc>; + }; +}; diff --git a/zephyr/program/nissa/yavilla/overlay.dtsi b/zephyr/program/nissa/yavilla/overlay.dtsi index b60ad2f476..c75ae9dd79 100644 --- a/zephyr/program/nissa/yavilla/overlay.dtsi +++ b/zephyr/program/nissa/yavilla/overlay.dtsi @@ -49,6 +49,16 @@ flags = ; handler = "power_button_interrupt"; }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; int_wp_l: wp_l { irq-pin = <&gpio_ec_wp_odl>; flags = ; @@ -59,6 +69,21 @@ flags = ; handler = "lid_interrupt"; }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_acc: lid_imu { + irq-pin = <&gpio_acc_int_l>; + flags = ; + handler = "bma4xx_interrupt"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; int_usb_c0: usb_c0 { irq-pin = <&gpio_usb_c0_int_odl>; flags = ; @@ -73,14 +98,9 @@ unused-pins { compatible = "unused-gpios"; - unused-gpios = <&gpioa 7 0>, - <&gpioc 0 0>, - <&gpioc 6 0>, + unused-gpios = <&gpioc 6 0>, <&gpiod 7 0>, <&gpioh 2 0>, - <&gpioi 6 0>, - <&gpioi 7 0>, - <&gpioj 0 0>, <&gpioj 3 0>, <&gpiok 7 GPIO_OUTPUT>; }; @@ -292,7 +312,7 @@ &i2c2 { label = "I2C_SENSOR"; - clock-frequency = ; + clock-frequency = ; pinctrl-0 = <&i2c2_clk_gpf6_default &i2c2_data_gpf7_default>; pinctrl-names = "default"; diff --git a/zephyr/program/nissa/yavilla/project.conf b/zephyr/program/nissa/yavilla/project.conf index 30818c4419..8011391adf 100644 --- a/zephyr/program/nissa/yavilla/project.conf +++ b/zephyr/program/nissa/yavilla/project.conf @@ -8,17 +8,11 @@ CONFIG_BOARD_YAVILLA=y CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI3=y CONFIG_PLATFORM_EC_KEYBOARD_REFRESH_ROW3=y -# Sensors: disabled; yavilla is clamshell-only -CONFIG_PLATFORM_EC_LID_ANGLE=n -CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=n -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=n -CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=n -CONFIG_PLATFORM_EC_ACCEL_FIFO=n -CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=n -CONFIG_PLATFORM_EC_GMR_TABLET_MODE=n -CONFIG_PLATFORM_EC_TABLET_MODE=n -CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=n -CONFIG_PLATFORM_EC_VOLUME_BUTTONS=n +# Sensors +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_DYNAMIC_MOTION_SENSOR_COUNT=y CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 # Keyboard diff --git a/zephyr/program/nissa/yavilla/project.overlay b/zephyr/program/nissa/yavilla/project.overlay index 97f431022c..40bbaec4bb 100644 --- a/zephyr/program/nissa/yavilla/project.overlay +++ b/zephyr/program/nissa/yavilla/project.overlay @@ -9,5 +9,6 @@ #include "fan.dtsi" #include "gpio.dtsi" #include "keyboard.dtsi" +#include "motionsense.dtsi" #include "overlay.dtsi" #include "power_signals.dtsi" diff --git a/zephyr/program/nissa/yavilla/src/board.c b/zephyr/program/nissa/yavilla/src/board.c index f89b92ebd8..feee5fa91f 100644 --- a/zephyr/program/nissa/yavilla/src/board.c +++ b/zephyr/program/nissa/yavilla/src/board.c @@ -3,14 +3,19 @@ * found in the LICENSE file. */ /* yavilla hardware configuration */ +#include "cros_cbi.h" #include "gpio/gpio_int.h" #include "hooks.h" +#include "motion_sense.h" +#include "tablet_mode.h" #include "task.h" +#include #include #include #include #include +#include #include LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); __override uint8_t board_get_usb_pd_port_count(void) @@ -22,10 +27,39 @@ __override uint8_t board_get_usb_pd_port_count(void) */ static void board_init(void) { + int ret; + uint32_t val; + + /* + * Retrieve the tablet config. + */ + ret = cros_cbi_get_fw_config(FW_TABLET, &val); + if (ret != 0) { + LOG_ERR("Error retrieving CBI FW_CONFIG field %d", FW_TABLET); + return; + } + /* * Enable USB-C interrupts. */ gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0)); gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1)); + + /* + * Disable tablet related interrupts for tablet absent DUT. + */ + if (val == FW_TABLET_ABSENT) { + motion_sensor_count = 0; + gmr_tablet_switch_disable(); + gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_imu)); + /* Base accel is not stuffed, don't allow line to float */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_imu_int_l), + GPIO_INPUT | GPIO_PULL_DOWN); + /* Lid accel is not stuffed, don't allow line to float */ + gpio_pin_configure_dt(GPIO_DT_FROM_NODELABEL(gpio_acc_int_l), + GPIO_INPUT | GPIO_PULL_DOWN); + LOG_INF("Clameshell: Disable motion sensors and gmr sensor!"); + } else + LOG_INF("Convertible!!!"); } -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_POST_I2C); -- cgit v1.2.1 From ef5d1e3f1d9dcabe007ccbbc71b81a85412e0087 Mon Sep 17 00:00:00 2001 From: Yu-An Chen Date: Tue, 16 May 2023 09:23:42 +0800 Subject: taranza: Enable ectool led control Enable ectool led control BUG=b:278167979 TEST=ectool led power white/off/auto Change-Id: I36f5aac2ff78aa6e68347ece6cc59eb87a3bb8b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4533460 Tested-by: Yu-An Chen Reviewed-by: Zhuohao Lee Commit-Queue: Yu-An Chen --- board/taranza/led.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/taranza/led.c b/board/taranza/led.c index 4f41c3c6c1..6101e9a263 100644 --- a/board/taranza/led.c +++ b/board/taranza/led.c @@ -59,6 +59,9 @@ int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) /* Called by hook task every TICK */ static void led_tick(void) { + if (!led_auto_control_is_enabled(EC_LED_ID_POWER_LED)) + return; + if (chipset_in_state(CHIPSET_STATE_ON)) led_set_color_power(LED_WHITE); else -- cgit v1.2.1 From 4291f8eefd66c0d64742f58dc1ae1c26c30427b2 Mon Sep 17 00:00:00 2001 From: Siyu Qin Date: Fri, 28 Apr 2023 16:02:11 +0800 Subject: battery: check the battery stable state when battery wake up Check the specific battery status to judge whether the battery is initialized and stable when the battery wakes up from ship mode. Use two MASKs to provide logical AND and logical OR options for different status. BUG=b:275392868 TEST=zmake build -a Change-Id: I7c5b4c9a74024846b6611ed49bf4823cf877469c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4486658 Reviewed-by: Mike Lee Tested-by: Siyu Qin Reviewed-by: Eric Yilun Lin Commit-Queue: Siyu Qin --- driver/battery/smart.c | 23 +++++++++++++++------ include/config.h | 33 ++++++++++++++++++++++++++++++ zephyr/Kconfig.battery | 43 +++++++++++++++++++++++++++++++++++++++ zephyr/shim/include/config_chip.h | 6 ++++++ 4 files changed, 99 insertions(+), 6 deletions(-) diff --git a/driver/battery/smart.c b/driver/battery/smart.c index b3d1787338..4d64c29efa 100644 --- a/driver/battery/smart.c +++ b/driver/battery/smart.c @@ -590,14 +590,25 @@ int battery_wait_for_stable(void) BATTERY_NO_RESPONSE_TIMEOUT); while (get_time().val < wait_timeout) { /* Starting pinging battery */ - if (battery_status(&status) == EC_SUCCESS) { - /* Battery is stable */ - CPRINTS("battery responded with status %x", status); - return EC_SUCCESS; + if (battery_status(&status) != EC_SUCCESS) { + msleep(25); /* clock stretching could hold 25ms */ + continue; + } + +#ifdef CONFIG_BATTERY_STBL_STAT + if (((status & CONFIG_BATT_ALARM_MASK1) == + CONFIG_BATT_ALARM_MASK1) || + ((status & CONFIG_BATT_ALARM_MASK2) == + CONFIG_BATT_ALARM_MASK2)) { + msleep(25); + continue; } - msleep(25); /* clock stretching could hold 25ms */ +#endif + /* Battery is stable */ + CPRINTS("battery responded with status %x", status); + return EC_SUCCESS; } - CPRINTS("battery not responding"); + CPRINTS("battery not responding with status %x", status); return EC_ERROR_NOT_POWERED; } diff --git a/include/config.h b/include/config.h index a3a2edb1ed..dfc684f278 100644 --- a/include/config.h +++ b/include/config.h @@ -664,6 +664,12 @@ */ #undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV +/* + * Check the specific battery status to judge whether the battery is + * initialized and stable when the battery wakes up from ship mode. + */ +#undef CONFIG_BATTERY_STBL_STAT + /* * Some batteries don't update full capacity timely or don't update it at all. * On such systems, compensation is required to guarantee remaining_capacity @@ -6411,6 +6417,33 @@ #define CONFIG_BATTERY_V1 #endif +/* + * Check the specific battery status to judge whether the battery is + * initialized and stable when the battery wakes up from ship mode. + * Use two MASKs to provide logical AND and logical OR options for different + * status. For example: + * + * Logical OR -- just check one of TCA/TDA mask: + * #define CONFIG_BATT_ALARM_MASK1 \ + * (STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM) + * #define CONFIG_BATT_ALARM_MASK2 0xFFFF + * + * Logical AND -- check both TCA/TDA mask: + * #define CONFIG_BATT_ALARM_MASK1 STATUS_TERMINATE_CHARGE_ALARM + * #define CONFIG_BATT_ALARM_MASK2 STATUS_TERMINATE_DISCHARGE_ALARM + * + * The default configuration is logical OR. + */ +#ifdef CONFIG_BATTERY_STBL_STAT +#ifndef CONFIG_BATT_ALARM_MASK1 +#define CONFIG_BATT_ALARM_MASK1 \ + (STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM) +#endif +#ifndef CONFIG_BATT_ALARM_MASK2 +#define CONFIG_BATT_ALARM_MASK2 0xFFFF +#endif +#endif + /*****************************************************************************/ /* Define derived USB PD Discharge common path */ #if defined(CONFIG_USB_PD_DISCHARGE_GPIO) || \ diff --git a/zephyr/Kconfig.battery b/zephyr/Kconfig.battery index 01d42567ab..2247e30cff 100644 --- a/zephyr/Kconfig.battery +++ b/zephyr/Kconfig.battery @@ -178,6 +178,49 @@ config PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV system tolerant of larger values of CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV. +config PLATFORM_EC_BATTERY_STBL_STAT + bool "Check whether the battery is initialized and stable" + help + Enables support for checking the specific battery status to + judge whether the battery is initialized and stable when the battery + wakes up from ship mode. Use two MASKs to provide logical AND and + logical OR options for different status. + + For example: + STATUS_TERMINATE_CHARGE_ALARM(TCA):0x4000 + STATUS_TERMINATE_DISCHARGE_ALARM(TDA):0x0800 + + Logical OR -- just check one of TCA/TDA mask: + CONFIG_PLATFORM_EC_BATT_ALARM_MASK1=(0x4000 | 0x0800) + CONFIG_PLATFORM_EC_BATT_ALARM_MASK2=0xFFFF + + Logical AND -- check both TCA/TDA mask: + CONFIG_PLATFORM_EC_BATT_ALARM_MASK1=0x4000 + CONFIG_PLATFORM_EC_BATT_ALARM_MASK2=0x0800 + + The default configuration is logical OR. + +if PLATFORM_EC_BATTERY_STBL_STAT + +config PLATFORM_EC_BATT_ALARM_MASK1 + hex "The battery status mask" + default 0x4800 + help + Use two MASKs to provide logical AND and logical OR options for different + status. Default mask 0x4800 means + (STATUS_TERMINATE_CHARGE_ALARM | STATUS_TERMINATE_DISCHARGE_ALARM), + any one of these two masks is set, the battery state can be considered + stable. + +config PLATFORM_EC_BATT_ALARM_MASK2 + hex "The battery status mask" + default 0xFFFF + help + Use two MASKs to provide logical AND and logical OR options for different + status. Default mask 0xFFFF means do not use this mask. + +endif # PLATFORM_EC_BATTERY_STBL_STAT + config PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON int "Minimum battery percentage for power on with an imbalanced pack" depends on PLATFORM_EC_BATTERY_MEASURE_IMBALANCE diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h index 132494d5f4..fa8e278996 100644 --- a/zephyr/shim/include/config_chip.h +++ b/zephyr/shim/include/config_chip.h @@ -297,7 +297,13 @@ CONFIG_PLATFORM_EC_BATTERY_MAX_IMBALANCE_MV #define CONFIG_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON \ CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_IMBALANCED_POWER_ON +#endif +#undef CONFIG_BATTERY_STBL_STAT +#ifdef CONFIG_PLATFORM_EC_BATTERY_STBL_STAT +#define CONFIG_BATTERY_STBL_STAT +#define CONFIG_BATT_ALARM_MASK1 CONFIG_PLATFORM_EC_BATT_ALARM_MASK1 +#define CONFIG_BATT_ALARM_MASK2 CONFIG_PLATFORM_EC_BATT_ALARM_MASK2 #endif #undef CONFIG_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV -- cgit v1.2.1 From 077f25a362b1789371fcb4e6aefbec81a6bd80f6 Mon Sep 17 00:00:00 2001 From: Siyu Qin Date: Fri, 12 May 2023 17:27:36 +0800 Subject: voltorb: enable checking battery stable status Check battery status TCA/TDA mask, any one of these two masks is set, the battery state can be considered stable. BUG=b:275392868 TEST=no "charge problem: batt params" in EC console when DUT wakes up from battery ship mode Change-Id: If8712e6e958bac9d9c0645b284a2569cdffae327 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4525879 Reviewed-by: Eric Yilun Lin Commit-Queue: Siyu Qin Tested-by: Siyu Qin Reviewed-by: Mike Lee --- zephyr/program/corsola/voltorb/project.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/program/corsola/voltorb/project.conf b/zephyr/program/corsola/voltorb/project.conf index d2693d0de8..19348b04cd 100644 --- a/zephyr/program/corsola/voltorb/project.conf +++ b/zephyr/program/corsola/voltorb/project.conf @@ -42,6 +42,7 @@ CONFIG_PLATFORM_EC_EXTPOWER_DEBOUNCE_MS=800 # Battery config CONFIG_PLATFORM_EC_BATT_FULL_CHIPSET_OFF_INPUT_LIMIT_MV=15000 CONFIG_PLATFORM_EC_SMART_BATTERY_OPTIONAL_MFG_FUNC=y +CONFIG_PLATFORM_EC_BATTERY_STBL_STAT=y # Remove debug options and features for FW QUAL CONFIG_PLATFORM_EC_SYSTEM_UNLOCKED=n -- cgit v1.2.1 From c1a1532a2ba081c7da1e430ee6b4798fd99cc63e Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Mon, 15 May 2023 18:00:01 +0800 Subject: omnigul: Remove TBT and USB4 define omnigul don't support Thunderbolt and USB4, remove them. BUG=b:282045980 TEST=omnigul didn't hang when connect two omnigul with typec cable Change-Id: Ied52af43231d7454b51d18b531c1d1bf0b54eaac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4530331 Tested-by: Logan Liao Code-Coverage: Kyle Lin Commit-Queue: Kyle Lin Reviewed-by: Kyle Lin Reviewed-by: Logan Liao --- board/omnigul/board.h | 9 --------- 1 file changed, 9 deletions(-) diff --git a/board/omnigul/board.h b/board/omnigul/board.h index 220d993667..fa5cc127db 100644 --- a/board/omnigul/board.h +++ b/board/omnigul/board.h @@ -70,8 +70,6 @@ #define CONFIG_USB_PORT_POWER_DUMB /* USB Type C and USB PD defines */ -#define CONFIG_USB_PD_REQUIRE_AP_MODE_ENTRY - #define CONFIG_IO_EXPANDER #define CONFIG_IO_EXPANDER_NCT38XX #define CONFIG_IO_EXPANDER_PORT_COUNT 1 @@ -169,13 +167,6 @@ #define USBC_PORT_C0_BB_RETIMER_I2C_ADDR 0x56 #define USBC_PORT_C2_BB_RETIMER_I2C_ADDR 0x57 -/* Enabling Thunderbolt-compatible mode */ -#define CONFIG_USB_PD_TBT_COMPAT_MODE - -/* Enabling USB4 mode */ -#define CONFIG_USB_PD_USB4 -#define CONFIG_USB_PD_DATA_RESET_MSG - /* Retimer */ #define CONFIG_USBC_RETIMER_FW_UPDATE -- cgit v1.2.1 From c1f50b036ae55fb0aa7e070f3e731e066eb09cf8 Mon Sep 17 00:00:00 2001 From: wangganxiang Date: Fri, 12 May 2023 14:26:41 +0800 Subject: starmie: Config the thermal sensor setting Add thermistor 1V9-100K-100K-4250B for ambient temperature. BUG=b:277309876 TEST=zmake build starmie Use ectool temps all to check can read thermistor temperature. Change-Id: Ia0786b2495f2b4f0d6d29d74cf176b9f61cff01a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4525658 Tested-by: Ganxiang Wang Reviewed-by: Mike Lee Reviewed-by: Sung-Chi Li Commit-Queue: Ganxiang Wang --- zephyr/include/cros/thermistor/thermistor.dtsi | 81 ++++++++++++++++++++++++++ zephyr/program/corsola/starmie/project.overlay | 43 ++++++++++++++ 2 files changed, 124 insertions(+) diff --git a/zephyr/include/cros/thermistor/thermistor.dtsi b/zephyr/include/cros/thermistor/thermistor.dtsi index fb86c4f79a..42eb07f483 100644 --- a/zephyr/include/cros/thermistor/thermistor.dtsi +++ b/zephyr/include/cros/thermistor/thermistor.dtsi @@ -386,4 +386,85 @@ sample-index = <12>; }; }; + + /omit-if-no-ref/ thermistor_1V8_100K_100K_4250B: + thermistor-1V9-100K-100K-4250B { + status = "disabled"; + compatible = "cros-ec,thermistor"; + scaling-factor = <7>; + num-pairs = <13>; + steinhart-reference-mv = <1800>; + steinhart-reference-res = <100000>; + + /* + * Data derived from Steinhart-Hart equation in a resistor + * divider circuit with Vdd=1800mV, R = 100Kohm, and thermistor + * (B = 4250, T0 = 357 K, nominal resistance (R0) = 100Kohm). + */ + sample-datum-0 { + milivolt = <(1406 / 7)>; + temp = <0>; + sample-index = <0>; + }; + sample-datum-1 { + milivolt = <(1219 / 7)>; + temp = <10>; + sample-index = <1>; + }; + sample-datum-2 { + milivolt = <(1007 / 7)>; + temp = <20>; + sample-index = <2>; + }; + sample-datum-3 { + milivolt = <(796 / 7)>; + temp = <30>; + sample-index = <3>; + }; + sample-datum-4 { + milivolt = <(606 / 7)>; + temp = <40>; + sample-index = <4>; + }; + sample-datum-5 { + milivolt = <( 449 / 7)>; + temp = <50>; + sample-index = <5>; + }; + sample-datum-6 { + milivolt = <( 327 / 7)>; + temp = <60>; + sample-index = <6>; + }; + sample-datum-7 { + milivolt = <( 237 / 7)>; + temp = <70>; + sample-index = <7>; + }; + sample-datum-8 { + milivolt = <( 172 / 7)>; + temp = <80>; + sample-index = <8>; + }; + sample-datum-9 { + milivolt = <( 147 / 7)>; + temp = <85>; + sample-index = <9>; + }; + sample-datum-10 { + milivolt = <( 125 / 7)>; + temp = <90>; + sample-index = <10>; + }; + sample-datum-11 { + milivolt = <( 107 / 7)>; + temp = <95>; + sample-index = <11>; + }; + sample-datum-12 { + milivolt = <( 92 / 7)>; + temp = <100>; + sample-index = <12>; + }; + }; }; diff --git a/zephyr/program/corsola/starmie/project.overlay b/zephyr/program/corsola/starmie/project.overlay index a4d69867a5..de79d92cdb 100644 --- a/zephyr/program/corsola/starmie/project.overlay +++ b/zephyr/program/corsola/starmie/project.overlay @@ -222,6 +222,39 @@ power-gpio-pin = <&pmic_ec_resetb>; }; }; + + named-adc-channels { + adc_temp_sensor_1: adc-temp-sensor-1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 6>; + }; + adc_temp_sensor_2: adc-temp-sensor-2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 7>; + }; + }; + + temp_sensor_1_thermistor: sensor-1-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_1V8_100K_100K_4250B>; + adc = <&adc_temp_sensor_1>; + }; + + temp_sensor_2_thermistor: sensor-2-thermistor { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_1V8_100K_100K_4250B>; + adc = <&adc_temp_sensor_2>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + temp_sensor_1 { + sensor = <&temp_sensor_1_thermistor>; + }; + temp_sensor_2 { + sensor = <&temp_sensor_2_thermistor>; + }; + }; }; &i2c0{ @@ -236,3 +269,13 @@ reg = <0x10>; }; }; + +&adc0{ + status = "okay"; + pinctrl-0 = <&adc0_ch6_gpi6_default>; + pinctrl-names = "default"; +}; + +&thermistor_1V8_100K_100K_4250B{ + status = "okay"; +}; -- cgit v1.2.1 From 63912887ea09683d096023da58f996f53926eb78 Mon Sep 17 00:00:00 2001 From: Devin Lu Date: Mon, 15 May 2023 14:50:41 +0800 Subject: vell: Sync up FW_CONFIG with config.star BUG=b:282189358 TEST=make BOARD=vell Change-Id: I7a37cf41e22982f354f74f0fe9dbe27673fb29f0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4530325 Commit-Queue: Boris Mittelberg Reviewed-by: Boris Mittelberg Tested-by: Devin Lu Reviewed-by: caveh jalali --- board/vell/fw_config.c | 36 ++++-------------------------------- board/vell/fw_config.h | 47 ++++++++++------------------------------------- 2 files changed, 14 insertions(+), 69 deletions(-) diff --git a/board/vell/fw_config.c b/board/vell/fw_config.c index bf5e29fe05..137c5c9f9a 100644 --- a/board/vell/fw_config.c +++ b/board/vell/fw_config.c @@ -12,20 +12,17 @@ #define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ##args) -static union brya_cbi_fw_config fw_config; +static union vell_cbi_fw_config fw_config; BUILD_ASSERT(sizeof(fw_config) == sizeof(uint32_t)); /* - * FW_CONFIG defaults for brya if the CBI.FW_CONFIG data is not + * FW_CONFIG defaults for vell if the CBI.FW_CONFIG data is not * initialized. */ -static const union brya_cbi_fw_config fw_config_defaults = { - .usb_db = DB_USB3_PS8815, - .kb_bl = KEYBOARD_BACKLIGHT_ENABLED, -}; +static const union vell_cbi_fw_config fw_config_defaults = {}; /**************************************************************************** - * Brya FW_CONFIG access + * Vell FW_CONFIG access */ void board_init_fw_config(void) { @@ -33,29 +30,4 @@ void board_init_fw_config(void) CPRINTS("CBI: Read FW_CONFIG failed, using board defaults"); fw_config = fw_config_defaults; } - - if (get_board_id() == 0) { - /* - * Early boards have a zero'd out FW_CONFIG, so replace - * it with a sensible default value. If DB_USB_ABSENT2 - * was used as an alternate encoding of DB_USB_ABSENT to - * avoid the zero check, then fix it. - */ - if (fw_config.raw_value == 0) { - CPRINTS("CBI: FW_CONFIG is zero, using board defaults"); - fw_config = fw_config_defaults; - } else if (fw_config.usb_db == DB_USB_ABSENT2) { - fw_config.usb_db = DB_USB_ABSENT; - } - } -} - -union brya_cbi_fw_config get_fw_config(void) -{ - return fw_config; -} - -enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void) -{ - return fw_config.usb_db; } diff --git a/board/vell/fw_config.h b/board/vell/fw_config.h index fea6c9a8da..324057a8e9 100644 --- a/board/vell/fw_config.h +++ b/board/vell/fw_config.h @@ -3,52 +3,25 @@ * found in the LICENSE file. */ -#ifndef __BOARD_BRYA_FW_CONFIG_H_ -#define __BOARD_BRYA_FW_CONFIG_H_ +#ifndef __BOARD_VELL_FW_CONFIG_H_ +#define __BOARD_VELL_FW_CONFIG_H_ #include /**************************************************************************** - * CBI FW_CONFIG layout for Brya board. + * CBI FW_CONFIG layout for Vell board. * - * Source of truth is the project/brya/brya/config.star configuration file. + * Source of truth is the project/brya/vell/config.star configuration file. */ - -enum ec_cfg_usb_db_type { - DB_USB_ABSENT = 0, - DB_USB3_PS8815 = 1, - DB_USB_ABSENT2 = 15 -}; - -enum ec_cfg_keyboard_backlight_type { - KEYBOARD_BACKLIGHT_DISABLED = 0, - KEYBOARD_BACKLIGHT_ENABLED = 1 -}; - -union brya_cbi_fw_config { +union vell_cbi_fw_config { struct { - enum ec_cfg_usb_db_type usb_db : 4; - uint32_t sd_db : 2; uint32_t lte_db : 1; - enum ec_cfg_keyboard_backlight_type kb_bl : 1; - uint32_t audio : 3; - uint32_t reserved_1 : 21; + uint32_t kb_color : 1; + uint32_t storage_nand : 1; + uint32_t wifi_sar_id : 2; + uint32_t reserved_1 : 27; }; uint32_t raw_value; }; -/** - * Read the cached FW_CONFIG. Guaranteed to have valid values. - * - * @return the FW_CONFIG for the board. - */ -union brya_cbi_fw_config get_fw_config(void); - -/** - * Get the USB daughter board type from FW_CONFIG. - * - * @return the USB daughter board type. - */ -enum ec_cfg_usb_db_type ec_cfg_usb_db_type(void); - -#endif /* __BOARD_BRYA_FW_CONFIG_H_ */ +#endif /* __BOARD_VELL_FW_CONFIG_H_ */ -- cgit v1.2.1 From 9383e02903200b02b312967c1517a3a0c5221f2b Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Mon, 15 May 2023 17:01:21 +0000 Subject: ec_openocd: flip the logic for verify, change to --no-verify The current verify option has to be used with --verify=0, which is a bit unintuitive. Replace it with a --no-verify, or -n. BUG=none TEST=./util/ec_openocd.py --board rex flash -n Change-Id: Ib2747c52b9a07c8ff3985dd0c7416331e2b042b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4534336 Tested-by: Fabio Baltieri Commit-Queue: Fabio Baltieri Reviewed-by: Robert Zieba --- util/ec_openocd.py | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/util/ec_openocd.py b/util/ec_openocd.py index 5da0479ed9..b8c9364bd8 100755 --- a/util/ec_openocd.py +++ b/util/ec_openocd.py @@ -1,8 +1,8 @@ #!/usr/bin/env python3 - # Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. + """ Flashes and debugs the EC through openocd """ @@ -123,7 +123,6 @@ def debug(interface, board, port, executable, attach): stderr=subprocess.STDOUT, preexec_fn=os.setsid, ) as openocd: - # Wait for OpenOCD to start, it'll open a port for GDB connections sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM) connected = False @@ -237,10 +236,10 @@ def main(): ) flash_parser.set_defaults(command="flash") flash_parser.add_argument( - "--verify", - "-v", - default=True, - help="Verify flash after writing image, defaults to true", + "--no-verify", + "-n", + action="store_true", + help="Do not verify flash after writing image", ) debug_parser = sub_parsers.add_parser( @@ -279,7 +278,7 @@ def main(): image_file = ( get_flash_file(args.board) if target_file is None else target_file ) - flash(args.interface, args.board, image_file, args.verify) + flash(args.interface, args.board, image_file, not args.no_verify) elif args.command == "debug": executable_file = ( get_executable_file(args.board) -- cgit v1.2.1 From 9ab5743831f081d1b4d161fe28be711ef2d01d4c Mon Sep 17 00:00:00 2001 From: Yi Chou Date: Mon, 8 May 2023 11:15:51 +0800 Subject: test_util.h: Add TEST_ASSERT_ARRAY_NE BUG=b:248508087 make runhosttests -j200 >/dev/null Change-Id: I7fa48a68bc8a56fb94649a4a0930ce83df6d9a84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4506541 Reviewed-by: Tom Hughes Commit-Queue: Yi Chou Tested-by: Yi Chou --- include/test_util.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/test_util.h b/include/test_util.h index 4f9869ab61..54da6a1d6c 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -19,6 +19,7 @@ extern "C" { #include "ec_commands.h" #include "math_util.h" #include "stack_trace.h" +#include "string.h" #ifdef CONFIG_ZTEST #include "ec_tasks.h" @@ -115,6 +116,19 @@ extern "C" { } \ } while (0) +#define TEST_ASSERT_ARRAY_NE(s, d, n) \ + do { \ + if (n < 0) \ + return EC_ERROR_UNKNOWN; \ + \ + if (memcmp(&s[0], &d[0], n) == 0) { \ + ccprintf("%s:%d: ASSERT_ARRAY_NE failed\n", __FILE__, \ + __LINE__); \ + task_dump_trace(); \ + return EC_ERROR_UNKNOWN; \ + } \ + } while (0) + #define TEST_ASSERT_MEMSET(d, c, n) \ do { \ if (n < 0) \ -- cgit v1.2.1 From 28939ffb30bdb1d9e6386cf390c982922ea9253d Mon Sep 17 00:00:00 2001 From: Yi Chou Date: Tue, 2 May 2023 15:18:58 +0800 Subject: boringssl: Implement sysrand from TRNG The boringssl doesn't include the TRNG implementation, we need our own CRYPTO_sysrand. BUG=b:248508087 TEST=make V=1 BOARD=bloonchipper -j TEST=./test/run_device_tests.py --board bloonchipper -t boringssl_crypto => PASS TEST=./test/run_device_tests.py --board dartmonkey -t boringssl_crypto => PASS Change-Id: I3136bcc96e09f674278bf338297d7bc0576e174c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4496289 Reviewed-by: Tom Hughes Commit-Queue: Yi Chou Tested-by: Yi Chou --- Makefile | 12 ++++++++++++ board/hatch_fp/build.mk | 1 + board/nocturne_fp/build.mk | 1 + board/nucleo-dartmonkey/build.mk | 1 + board/nucleo-f412zg/build.mk | 1 + board/nucleo-h743zi/build.mk | 1 + test/boringssl_crypto.cc | 35 ++++++++++++++++++++++++++++++++++ test/boringssl_crypto.tasklist | 9 +++++++++ test/build.mk | 2 ++ test/run_device_tests.py | 1 + test/test_config.h | 4 ++++ third_party/boringssl/common/build.mk | 8 ++++++++ third_party/boringssl/common/sysrand.c | 20 +++++++++++++++++++ 13 files changed, 96 insertions(+) create mode 100644 test/boringssl_crypto.cc create mode 100644 test/boringssl_crypto.tasklist create mode 100644 third_party/boringssl/common/build.mk create mode 100644 third_party/boringssl/common/sysrand.c diff --git a/Makefile b/Makefile index a8b282c613..f72eb9b65a 100644 --- a/Makefile +++ b/Makefile @@ -290,6 +290,11 @@ include test/build.mk include util/build.mk include util/lock/build.mk + +ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) +include third_party/boringssl/common/build.mk +endif + includes+=$(includes-y) # Wrapper for fetching all the sources relevant to this build @@ -326,6 +331,10 @@ all-obj-$(1)+=$(call objs_from_dir_p,fuzz,$(PROJECT),$(1)) else all-obj-$(1)+=$(call objs_from_dir_p,test,$(PROJECT),$(1)) endif +ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) +all-obj-$(1)+= \ + $(call objs_from_dir_p,third_party/boringssl/common,boringssl,$(1)) +endif endef # Get all sources to build @@ -372,6 +381,9 @@ dirs+=builtin else dirs+=libc endif +ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) +dirs+=third_party/boringssl/common +endif common_dirs=util ifeq ($(custom-ro_objs-y),) diff --git a/board/hatch_fp/build.mk b/board/hatch_fp/build.mk index 5e7af56ae2..ed9809843b 100644 --- a/board/hatch_fp/build.mk +++ b/board/hatch_fp/build.mk @@ -30,6 +30,7 @@ test-list-y=\ aes \ always_memset \ benchmark \ + boringssl_crypto \ cec \ compile_time_macros \ cortexm_fpu \ diff --git a/board/nocturne_fp/build.mk b/board/nocturne_fp/build.mk index e36309c4f0..6bf33696d5 100644 --- a/board/nocturne_fp/build.mk +++ b/board/nocturne_fp/build.mk @@ -30,6 +30,7 @@ test-list-y=\ aes \ always_memset \ benchmark \ + boringssl_crypto \ cec \ compile_time_macros \ cortexm_fpu \ diff --git a/board/nucleo-dartmonkey/build.mk b/board/nucleo-dartmonkey/build.mk index fbf78d16b7..de08959fa9 100644 --- a/board/nucleo-dartmonkey/build.mk +++ b/board/nucleo-dartmonkey/build.mk @@ -13,6 +13,7 @@ board-y+=fpsensor_detect.o test-list-y=\ abort \ aes \ + boringssl_crypto \ cec \ compile_time_macros \ crc \ diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk index 8299781a6f..c31e640099 100644 --- a/board/nucleo-f412zg/build.mk +++ b/board/nucleo-f412zg/build.mk @@ -12,6 +12,7 @@ board-y=board.o test-list-y=\ abort \ aes \ + boringssl_crypto \ cec \ compile_time_macros \ crc \ diff --git a/board/nucleo-h743zi/build.mk b/board/nucleo-h743zi/build.mk index 575a6d5da3..932793898a 100644 --- a/board/nucleo-h743zi/build.mk +++ b/board/nucleo-h743zi/build.mk @@ -12,6 +12,7 @@ board-y=board.o test-list-y=\ abort \ aes \ + boringssl \ cec \ compile_time_macros \ crc \ diff --git a/test/boringssl_crypto.cc b/test/boringssl_crypto.cc new file mode 100644 index 0000000000..bc7bd5dffe --- /dev/null +++ b/test/boringssl_crypto.cc @@ -0,0 +1,35 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "openssl/bn.h" +#include "openssl/ec.h" +#include "openssl/mem.h" +#include "openssl/obj_mac.h" +#include "openssl/rand.h" +#include "test_util.h" +#include "util.h" + +test_static enum ec_error_list test_rand(void) +{ + constexpr uint8_t zero[256] = { 0 }; + uint8_t buf1[256]; + uint8_t buf2[256]; + + RAND_bytes(buf1, sizeof(buf1)); + RAND_bytes(buf2, sizeof(buf2)); + + TEST_ASSERT_ARRAY_NE(buf1, zero, sizeof(zero)); + TEST_ASSERT_ARRAY_NE(buf2, zero, sizeof(zero)); + TEST_ASSERT_ARRAY_NE(buf1, buf2, sizeof(buf1)); + + return EC_SUCCESS; +} + +extern "C" void run_test(int argc, const char **argv) +{ + RUN_TEST(test_rand); + test_print_result(); +} diff --git a/test/boringssl_crypto.tasklist b/test/boringssl_crypto.tasklist new file mode 100644 index 0000000000..d1920322a9 --- /dev/null +++ b/test/boringssl_crypto.tasklist @@ -0,0 +1,9 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * See CONFIG_TASK_LIST in config.h for details. + */ +#define CONFIG_TEST_TASK_LIST diff --git a/test/build.mk b/test/build.mk index d948fd5f6e..d90e8daf26 100644 --- a/test/build.mk +++ b/test/build.mk @@ -28,6 +28,7 @@ test-list-host += benchmark test-list-host += bklight_lid test-list-host += bklight_passthru test-list-host += body_detection +test-list-host += boringssl_crypto test-list-host += button test-list-host += cbi test-list-host += cbi_wp @@ -181,6 +182,7 @@ benchmark-y=benchmark.o bklight_lid-y=bklight_lid.o bklight_passthru-y=bklight_passthru.o body_detection-y=body_detection.o body_detection_data_literals.o motion_common.o +boringssl_crypto-y=boringssl_crypto.o button-y=button.o cbi-y=cbi.o cbi_wp-y=cbi_wp.o diff --git a/test/run_device_tests.py b/test/run_device_tests.py index dc454527e7..e874d08bb7 100755 --- a/test/run_device_tests.py +++ b/test/run_device_tests.py @@ -230,6 +230,7 @@ class AllTests: TestConfig(test_name="aes"), TestConfig(test_name="always_memset"), TestConfig(test_name="benchmark"), + TestConfig(test_name="boringssl_crypto"), TestConfig(test_name="cec"), TestConfig(test_name="cortexm_fpu"), TestConfig(test_name="crc"), diff --git a/test/test_config.h b/test/test_config.h index 51c15f4c8c..033ee966b7 100644 --- a/test/test_config.h +++ b/test/test_config.h @@ -114,6 +114,10 @@ #define CONFIG_SHA256 #endif +#if defined(TEST_BORINGSSL_CRYPTO) +#define CONFIG_BORINGSSL_CRYPTO +#endif + #ifdef TEST_ROLLBACK_SECRET #define CONFIG_ROLLBACK #define CONFIG_ROLLBACK_SECRET_SIZE 32 diff --git a/third_party/boringssl/common/build.mk b/third_party/boringssl/common/build.mk new file mode 100644 index 0000000000..b7848d121b --- /dev/null +++ b/third_party/boringssl/common/build.mk @@ -0,0 +1,8 @@ +# Copyright 2023 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# EC OS Support Files for BoringSSL +# + +boringssl-y+=sysrand.o diff --git a/third_party/boringssl/common/sysrand.c b/third_party/boringssl/common/sysrand.c new file mode 100644 index 0000000000..74e058f892 --- /dev/null +++ b/third_party/boringssl/common/sysrand.c @@ -0,0 +1,20 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Implement the boringssl sysrand from EC TRNG. */ + +#include "trng.h" + +void CRYPTO_sysrand(uint8_t *out, size_t requested) +{ + trng_init(); + trng_rand_bytes(out, requested); + trng_exit(); +} + +void CRYPTO_sysrand_for_seed(uint8_t *out, size_t requested) +{ + return CRYPTO_sysrand(out, requested); +} -- cgit v1.2.1 From d20b09e533f7190284df1f60c60b9430f7ba0dd5 Mon Sep 17 00:00:00 2001 From: Yi Chou Date: Fri, 5 May 2023 10:18:41 +0800 Subject: boringssl: Add elliptic curve key helpers BUG=b:248508087 TEST=make V=1 BOARD=bloonchipper -j TEST=./test/run_device_tests.py --board bloonchipper -t boringssl_crypto => PASS TEST=./test/run_device_tests.py --board dartmonkey -t boringssl_crypto => PASS Change-Id: Ifdca7743c09910d413407be986e9d959e5b90479 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4505560 Tested-by: Yi Chou Commit-Queue: Yi Chou Reviewed-by: Tom Hughes --- Makefile | 3 +++ crypto/build.mk | 8 ++++++++ crypto/elliptic_curve_key.cc | 24 ++++++++++++++++++++++++ include/crypto/elliptic_curve_key.h | 20 ++++++++++++++++++++ test/boringssl_crypto.cc | 31 +++++++++++++++++++++++++++++++ 5 files changed, 86 insertions(+) create mode 100644 crypto/build.mk create mode 100644 crypto/elliptic_curve_key.cc create mode 100644 include/crypto/elliptic_curve_key.h diff --git a/Makefile b/Makefile index f72eb9b65a..812b5dc2c4 100644 --- a/Makefile +++ b/Makefile @@ -293,6 +293,7 @@ include util/lock/build.mk ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) include third_party/boringssl/common/build.mk +include crypto/build.mk endif includes+=$(includes-y) @@ -334,6 +335,7 @@ endif ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) all-obj-$(1)+= \ $(call objs_from_dir_p,third_party/boringssl/common,boringssl,$(1)) +all-obj-$(1)+= $(call objs_from_dir_p,crypto,crypto,$(1)) endif endef @@ -383,6 +385,7 @@ dirs+=libc endif ifeq ($(CONFIG_BORINGSSL_CRYPTO), y) dirs+=third_party/boringssl/common +dirs+=crypto endif common_dirs=util diff --git a/crypto/build.mk b/crypto/build.mk new file mode 100644 index 0000000000..fbbfed1ac9 --- /dev/null +++ b/crypto/build.mk @@ -0,0 +1,8 @@ +# Copyright 2023 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Crypto related Files +# + +crypto-y+=elliptic_curve_key.o diff --git a/crypto/elliptic_curve_key.cc b/crypto/elliptic_curve_key.cc new file mode 100644 index 0000000000..53741d0944 --- /dev/null +++ b/crypto/elliptic_curve_key.cc @@ -0,0 +1,24 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "crypto/elliptic_curve_key.h" +#include "openssl/ec_key.h" +#include "openssl/mem.h" +#include "openssl/obj_mac.h" + +bssl::UniquePtr generate_elliptic_curve_key() +{ + bssl::UniquePtr key( + EC_KEY_new_by_curve_name(NID_X9_62_prime256v1)); + if (key == nullptr) { + return nullptr; + } + + if (EC_KEY_generate_key(key.get()) != 1) { + return nullptr; + } + + return key; +} diff --git a/include/crypto/elliptic_curve_key.h b/include/crypto/elliptic_curve_key.h new file mode 100644 index 0000000000..1e56f5d428 --- /dev/null +++ b/include/crypto/elliptic_curve_key.h @@ -0,0 +1,20 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Helpers for the boringssl elliptic curve key interface. */ + +#ifndef __CROS_EC_ELLIPTIC_CURVE_KEY_H +#define __CROS_EC_ELLIPTIC_CURVE_KEY_H + +#include "openssl/ec_key.h" +#include "openssl/mem.h" + +/** + * Generate a p256 ECC key. + * @return key on success, nullptr on failure + */ +bssl::UniquePtr generate_elliptic_curve_key(); + +#endif /* __CROS_EC_ELLIPTIC_CURVE_KEY_H */ diff --git a/test/boringssl_crypto.cc b/test/boringssl_crypto.cc index bc7bd5dffe..c04b391854 100644 --- a/test/boringssl_crypto.cc +++ b/test/boringssl_crypto.cc @@ -4,6 +4,7 @@ */ #include "common.h" +#include "crypto/elliptic_curve_key.h" #include "openssl/bn.h" #include "openssl/ec.h" #include "openssl/mem.h" @@ -28,8 +29,38 @@ test_static enum ec_error_list test_rand(void) return EC_SUCCESS; } +test_static enum ec_error_list test_ecc_keygen(void) +{ + bssl::UniquePtr key1 = generate_elliptic_curve_key(); + + TEST_NE(key1.get(), nullptr, "%p"); + + /* The generated key should be valid.*/ + TEST_EQ(EC_KEY_check_key(key1.get()), 1, "%d"); + + bssl::UniquePtr key2 = generate_elliptic_curve_key(); + + TEST_NE(key2.get(), nullptr, "%p"); + + /* The generated key should be valid. */ + TEST_EQ(EC_KEY_check_key(key2.get()), 1, "%d"); + + const BIGNUM *priv1 = EC_KEY_get0_private_key(key1.get()); + const BIGNUM *priv2 = EC_KEY_get0_private_key(key2.get()); + + /* The generated keys should not be the same. */ + TEST_NE(BN_cmp(priv1, priv2), 0, "%d"); + + /* The generated keys should not be zero. */ + TEST_EQ(BN_is_zero(priv1), 0, "%d"); + TEST_EQ(BN_is_zero(priv2), 0, "%d"); + + return EC_SUCCESS; +} + extern "C" void run_test(int argc, const char **argv) { RUN_TEST(test_rand); + RUN_TEST(test_ecc_keygen); test_print_result(); } -- cgit v1.2.1 From 45397393246d14872a895cbefcb219bc5e31fc6f Mon Sep 17 00:00:00 2001 From: Ruihai Zhou Date: Wed, 10 May 2023 19:03:31 +0800 Subject: motion_sense: Fix null pointer reference in gesture detection The motion_sense_fifo_stage_data with NULL were removed in CL:4499747. But we need to stage and commit the motion state changed to activity sensor for body detection on the ap side. Revert the change and Add null pointer check in motion_sense_fifo_stage_data and fifo_stage_unit to fix it. BUG=b:272655176 TEST=./twister -v -i -p native_posix -p unit_testing -s drivers/drivers.body_detection TEST=received User proximity: Near/Far event from powerd log Change-Id: I1ef882f25e07fa17d879d8b0a4b9ffe211b071e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4520740 Tested-by: Ruihai Zhou Commit-Queue: Tim Van Patten Reviewed-by: Sung-Chi Li Reviewed-by: Tim Van Patten --- common/body_detection.c | 13 +++++++++++++ common/motion_sense.c | 41 ++++++++++++++++++++++++++++++++++++++++- common/motion_sense_fifo.c | 5 ++++- 3 files changed, 57 insertions(+), 2 deletions(-) diff --git a/common/body_detection.c b/common/body_detection.c index d16e83df00..646bc6d740 100644 --- a/common/body_detection.c +++ b/common/body_detection.c @@ -102,6 +102,19 @@ void body_detect_change_state(enum body_detect_states state, bool spoof) { if (IS_ENABLED(CONFIG_ACCEL_SPOOF_MODE) && spoof_enable && !spoof) return; + if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { + struct ec_response_motion_sensor_data vector = { + .flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO, + .activity_data = { + .activity = MOTIONSENSE_ACTIVITY_BODY_DETECTION, + .state = state, + }, + .sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID, + }; + motion_sense_fifo_stage_data(&vector, NULL, 0, + __hw_clock_source_read()); + motion_sense_fifo_commit_data(); + } /* change the motion state */ motion_state = state; if (state == BODY_DETECTION_ON_BODY) { diff --git a/common/motion_sense.c b/common/motion_sense.c index 16a37d37a5..546034c7e2 100644 --- a/common/motion_sense.c +++ b/common/motion_sense.c @@ -698,6 +698,26 @@ static void check_and_queue_gestures(uint32_t *event) if (IS_ENABLED(CONFIG_GESTURE_SENSOR_DOUBLE_TAP) && (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( MOTIONSENSE_ACTIVITY_DOUBLE_TAP))) { + if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { + struct ec_response_motion_sensor_data vector; + + vector.flags = MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO; + /* + * Send events to the FIFO + * AP is ignoring double tap event, do no wake up and no + * automatic disable. + */ + if (IS_ENABLED( + CONFIG_GESTURE_SENSOR_DOUBLE_TAP_FOR_HOST)) + vector.flags |= MOTIONSENSE_SENSOR_FLAG_WAKEUP; + vector.activity_data.activity = + MOTIONSENSE_ACTIVITY_DOUBLE_TAP; + vector.activity_data.state = 1 /* triggered */; + vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID; + motion_sense_fifo_stage_data(&vector, NULL, 0, + __hw_clock_source_read()); + motion_sense_fifo_commit_data(); + } /* Call board specific function to process tap */ sensor_board_proc_double_tap(); } @@ -705,7 +725,20 @@ static void check_and_queue_gestures(uint32_t *event) (*event & TASK_EVENT_MOTION_ACTIVITY_INTERRUPT( MOTIONSENSE_ACTIVITY_SIG_MOTION))) { struct motion_sensor_t *activity_sensor; - + if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION)) { + struct ec_response_motion_sensor_data vector; + + /* Send events to the FIFO */ + vector.flags = MOTIONSENSE_SENSOR_FLAG_WAKEUP | + MOTIONSENSE_SENSOR_FLAG_BYPASS_FIFO; + vector.activity_data.activity = + MOTIONSENSE_ACTIVITY_SIG_MOTION; + vector.activity_data.state = 1 /* triggered */; + vector.sensor_num = MOTION_SENSE_ACTIVITY_SENSOR_ID; + motion_sense_fifo_stage_data(&vector, NULL, 0, + __hw_clock_source_read()); + motion_sense_fifo_commit_data(); + } /* Disable further detection */ activity_sensor = &motion_sensors[CONFIG_GESTURE_SIGMO_SENSOR]; activity_sensor->drv->manage_activity( @@ -730,6 +763,12 @@ static void check_and_queue_gestures(uint32_t *event) (*motion_orientation_ptr(sensor) != MOTIONSENSE_ORIENTATION_UNKNOWN)) { motion_orientation_update(sensor); + vector.activity_data.state = + *motion_orientation_ptr(sensor); + motion_sense_fifo_stage_data( + &vector, NULL, 0, + __hw_clock_source_read()); + motion_sense_fifo_commit_data(); if (IS_ENABLED(CONFIG_DEBUG_ORIENTATION)) { static const char *const mode[] = { "Landscape", "Portrait", diff --git a/common/motion_sense_fifo.c b/common/motion_sense_fifo.c index fd1bfda88c..1a7303bc79 100644 --- a/common/motion_sense_fifo.c +++ b/common/motion_sense_fifo.c @@ -271,6 +271,9 @@ static void fifo_stage_unit(struct ec_response_motion_sensor_data *data, struct queue_chunk chunk; int i; + if (valid_data > 0 && !sensor) + return; + mutex_lock(&g_sensor_mutex); for (i = 0; i < valid_data; i++) @@ -460,7 +463,7 @@ void motion_sense_fifo_stage_data(struct ec_response_motion_sensor_data *data, fifo_staged.read_ts = __hw_clock_source_read(); fifo_stage_timestamp(time, data->sensor_num); } - if (sensor->config[SENSOR_CONFIG_AP].ec_rate > 0 && + if (sensor && sensor->config[SENSOR_CONFIG_AP].ec_rate > 0 && time_after(time, ts_last_int[id] + sensor->config[SENSOR_CONFIG_AP].ec_rate - MOTION_SENSOR_INT_ADJUSTMENT_US)) { -- cgit v1.2.1 From 32a3d94e879efebef135062342fdbd9dae8ec463 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 12 May 2023 10:25:48 -0600 Subject: AMD Mux Emul: Stabilize delayed mux set code The current emulator relies on timing in order to delay mux sets. However, this can lead to some surprising mismatches in time between the emulator and test (such as the write completing during a subsequent test case). Instead, delay by the number of reads the driver has done. BUG=b:234771735 TEST=./twister -s drivers/drivers.amd_fp6_usb_mux Change-Id: I71c78348e29b70c479da8009b8a085cf4e57c188 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4528795 Reviewed-by: Jeremy Bettis Commit-Queue: Diana Z Tested-by: Diana Z --- zephyr/emul/emul_amd_fp6.c | 18 ++++++++++-------- zephyr/include/emul/emul_amd_fp6.h | 9 ++++++--- .../drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c | 2 +- 3 files changed, 17 insertions(+), 12 deletions(-) diff --git a/zephyr/emul/emul_amd_fp6.c b/zephyr/emul/emul_amd_fp6.c index dfb763e1c8..b0b618fd6a 100644 --- a/zephyr/emul/emul_amd_fp6.c +++ b/zephyr/emul/emul_amd_fp6.c @@ -28,8 +28,8 @@ enum amd_fp6_read_bytes { struct amd_fp6_data { struct i2c_common_emul_data common; - int64_t finish_delay; /* How long before mux set "completes"? */ - int64_t set_time; /* Time of last set call */ + int finish_delay; /* How many reads before mux set "completes"? */ + int waiting_reads; /* How many reads have we waited to complete? */ uint8_t last_mux_set; /* Last value of mux set call */ uint8_t regs[AMD_FP6_MAX_REG]; }; @@ -58,11 +58,11 @@ void amd_fp6_emul_reset_regs(const struct emul *emul) data->regs[AMD_FP6_PORT1] = 0; } -void amd_fp6_emul_set_delay(const struct emul *emul, int delay_ms) +void amd_fp6_emul_set_delay(const struct emul *emul, int delay_reads) { struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data; - data->finish_delay = delay_ms; + data->finish_delay = delay_reads; } void amd_fp6_emul_set_xbar(const struct emul *emul, bool ready) @@ -87,11 +87,11 @@ static int amd_fp6_emul_read(const struct emul *emul, int reg, uint8_t *val, /* Decide if we've finally finished our operation */ if (pos == AMD_FP6_PORT0 && data->finish_delay > 0) { - int64_t uptime = k_uptime_delta(&data->set_time); + data->waiting_reads++; if (((regs[pos] >> AMD_FP6_MUX_PORT_STATUS_OFFSET) == AMD_FP6_MUX_PORT_CMD_BUSY) && - (uptime >= data->finish_delay)) + (data->waiting_reads >= data->finish_delay)) regs[pos] = amd_fp6_emul_mux_complete(data->last_mux_set); } @@ -113,11 +113,13 @@ static int amd_fp6_emul_write(const struct emul *emul, int reg, uint8_t val, data->last_mux_set = val; - if (data->finish_delay == 0) + if (data->finish_delay == 0) { regs[AMD_FP6_PORT0] = amd_fp6_emul_mux_complete(val); - else + } else { + data->waiting_reads = 0; regs[AMD_FP6_PORT0] = AMD_FP6_MUX_PORT_CMD_BUSY << AMD_FP6_MUX_PORT_STATUS_OFFSET; + } return 0; } diff --git a/zephyr/include/emul/emul_amd_fp6.h b/zephyr/include/emul/emul_amd_fp6.h index 6c63a6caab..04dcd5dd31 100644 --- a/zephyr/include/emul/emul_amd_fp6.h +++ b/zephyr/include/emul/emul_amd_fp6.h @@ -29,10 +29,13 @@ void amd_fp6_emul_set_xbar(const struct emul *emul, bool ready); * Set how long a command will take to complete. On a real system this can be * anywhere from 50-100ms and the datasheet defines it can take up to 250ms. * + * Getting timing to sync consistently in unit testing is difficult, so use the + * number of reads to wait instead. + * * @param emul - AMD FP6 emulator data - * @param delay_ms - how long after a mux set to wait before reporting the - * status of the set as complete. + * @param delay_reads - how long after a mux set to wait before reporting the + * status of the set as complete (in number of reads) */ -void amd_fp6_emul_set_delay(const struct emul *emul, int delay_ms); +void amd_fp6_emul_set_delay(const struct emul *emul, int delay_reads); #endif diff --git a/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c b/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c index d900b2d3c2..8d8a6982cf 100644 --- a/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c +++ b/zephyr/test/drivers/amd_fp6_usb_mux/src/amd_fp6_usb_mux_test.c @@ -140,7 +140,7 @@ ZTEST_F(amd_fp6_usb_mux, test_chipset_reset) ZTEST_F(amd_fp6_usb_mux, test_long_command) { /* Allow the mux to take a while, like on real systems */ - amd_fp6_emul_set_delay(fixture->amd_fp6_emul, 100); + amd_fp6_emul_set_delay(fixture->amd_fp6_emul, 6); /* Send a basic set to USB mode */ usb_mux_set(TEST_PORT, USB_PD_MUX_USB_ENABLED, USB_SWITCH_CONNECT, 1); -- cgit v1.2.1 From cfc740514c3de776534d22673ebf05fe8c906c5b Mon Sep 17 00:00:00 2001 From: Abe Levkoy Date: Mon, 15 May 2023 12:46:52 -0600 Subject: TCPMv2: Do not attempt Enter_USB under PD 2.0 If the port partner is not PD 3.0 or higher, do not consider it to support USB4/Enter_USB. If the AP requests USB4 entry, disregard the request and consider mode entry complete. Avoid repeatedly sending Enter_USB to a PD 2.0 partner. BUG=b:279421317 TEST=twister -s drivers/drivers.usbc_usb4_mode Change-Id: I3e82738f816e6dd5af24d627b6cd971a34d74586 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4533369 Commit-Queue: Abe Levkoy Tested-by: Abe Levkoy Reviewed-by: Jameson Thies --- common/usbc/usb_mode.c | 4 +++ .../drivers/usbc_usb4_mode/src/usbc_usb4_mode.c | 38 ++++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/common/usbc/usb_mode.c b/common/usbc/usb_mode.c index 017f89fc74..157c1b1f04 100644 --- a/common/usbc/usb_mode.c +++ b/common/usbc/usb_mode.c @@ -20,6 +20,7 @@ #include "usb_pd_dpm_sm.h" #include "usb_pd_tcpm.h" #include "usb_pe_sm.h" +#include "usb_prl_sm.h" #include "usb_tbt_alt_mode.h" #include "usbc_ppc.h" @@ -169,6 +170,9 @@ bool enter_usb_port_partner_is_capable(int port) if (usb4_state[port] == USB4_INACTIVE) return false; + if (prl_get_rev(port, TCPCI_MSG_SOP) < PD_REV30) + return false; + if (!PD_PRODUCT_IS_USB4(disc->identity.product_t1.raw_value)) return false; diff --git a/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c b/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c index 4c21aaeac4..25fcff61e1 100644 --- a/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c +++ b/zephyr/test/drivers/usbc_usb4_mode/src/usbc_usb4_mode.c @@ -259,6 +259,44 @@ ZTEST_F(usbc_usb4_mode, test_verify_usb4_passive_entry_exit) USB_PD_MUX_USB_ENABLED, "Failed to see USB set"); } +/* If the partner claims to support USB4, but communication is only PD 2.0, the + * EC should disregard a request to enter USB4 from the host. + */ +ZTEST_F(usbc_usb4_mode, test_verify_usb4_pd2_no_entry) +{ + struct ec_response_typec_status status; + + tcpci_partner_init(&fixture->partner, PD_REV20); + fixture->partner.cable = &passive_usb4; + connect_sink_to_port(&fixture->partner, fixture->tcpci_emul, + fixture->charger_emul); + + /* Instruct partner port to accept Enter_USB message */ + fixture->partner.enter_usb_accept = true; + + /* Verify that we properly identify a USB4 capable passive cable */ + verify_cable_found(fixture->partner.cable); + + status = host_cmd_typec_status(TEST_PORT); + zassert_equal((status.mux_state & USB_MUX_CHECK_MASK), + USB_PD_MUX_USB_ENABLED, "Unexpected starting mux: 0x%02x", + status.mux_state); + + host_cmd_typec_control_enter_mode(TEST_PORT, TYPEC_MODE_USB4); + k_sleep(K_SECONDS(1)); + + /* PD 2.0 doesn't include Enter_USB, so it's not possible to enter USB4 + * mode. A Discover Identity ACK indicating support for USB4 isn't even + * valid under PD 2.0. If the host nevertheless commands the EC to enter + * USB4, the EC should not attempt to do so. + */ + status = host_cmd_typec_status(TEST_PORT); + zassert_equal((status.mux_state & USB_MUX_CHECK_MASK), + USB_PD_MUX_USB_ENABLED, "Failed to see USB still set"); + zassert_not_equal((status.mux_state & USB_MUX_CHECK_MASK), + USB_PD_MUX_USB4_ENABLED, "Unexpected USB4 mode set"); +} + /* * TODO(b/260095516): This test suite is only testing the default good case, and * one error case where the cable doesn't support USB4. This suite needs to be -- cgit v1.2.1 From 318306b3a82aa941abe0a559e87d66009f0663c9 Mon Sep 17 00:00:00 2001 From: Jeremy Bettis Date: Tue, 16 May 2023 20:31:08 +0000 Subject: ec: Add #line in include/lid_switch.h Work around coreboot GCC preprocessor bug. BUG=b:272518464 TEST=gcc -E Change-Id: Ic95717cab141d76a20d45a16126ac37a8859829e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4540107 Reviewed-by: Al Semjonovs Commit-Queue: Jeremy Bettis Auto-Submit: Jeremy Bettis Tested-by: Jeremy Bettis --- include/lid_switch.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/lid_switch.h b/include/lid_switch.h index 3d639b5782..8b62d89949 100644 --- a/include/lid_switch.h +++ b/include/lid_switch.h @@ -5,6 +5,12 @@ /* Lid switch API for Chrome EC */ +/* + * TODO(b/272518464): Work around coreboot GCC preprocessor bug. + * #line marks the *next* line, so it is off by one. + */ +#line 13 + #ifndef __CROS_EC_LID_SWITCH_H #define __CROS_EC_LID_SWITCH_H -- cgit v1.2.1 From b34dc2ae9022e2fbb57ae6477891ff32954c62fd Mon Sep 17 00:00:00 2001 From: Tristan Honscheid Date: Tue, 16 May 2023 14:33:26 -0600 Subject: presubmit: Require bug in LOW_COVERAGE_REASON Enforce having a bug listed in the LOW_COVERAGE_REASON to track the issue that impedes coverage for that specific CL. This encourages developers to go back and fix those problems. Also update the documentation. BUG=None TEST=util/check_low_coverage_reason.py Change-Id: If35f918b11771d10944e0b6e7a4aeeba84e05eaf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4537010 Reviewed-by: Jeremy Bettis Commit-Queue: Jeremy Bettis Auto-Submit: Tristan Honscheid Tested-by: Tristan Honscheid --- PRESUBMIT.cfg | 1 + docs/chromeos-ec-firmware-test-requirements.md | 3 +- util/check_low_coverage_reason.py | 58 ++++++++++++++++++++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) create mode 100755 util/check_low_coverage_reason.py diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg index 8cc7ddf2cd..c925185270 100644 --- a/PRESUBMIT.cfg +++ b/PRESUBMIT.cfg @@ -38,3 +38,4 @@ twister_test_tags = util/twister_tags.py --validate-files ${PRESUBMIT_FILES} check_zephyr_project_config = util/check_zephyr_project_config.py -d ${PRESUBMIT_FILES} zephyr_check_compliance = util/zephyr_check_compliance.py ${PRESUBMIT_COMMIT} zephyr_check_testcase_yaml = ./util/zephyr_check_testcase_yaml.py --commit ${PRESUBMIT_COMMIT} ${PRESUBMIT_FILES} +low_coverage_reason = ./util/check_low_coverage_reason.py ${PRESUBMIT_COMMIT} diff --git a/docs/chromeos-ec-firmware-test-requirements.md b/docs/chromeos-ec-firmware-test-requirements.md index 2e8b461eb6..721021275a 100644 --- a/docs/chromeos-ec-firmware-test-requirements.md +++ b/docs/chromeos-ec-firmware-test-requirements.md @@ -56,7 +56,8 @@ reports locally on your machine. In limited cases, you may amend your commit message to include the `LOW_COVERAGE_REASON` tag. This tag bypasses the code coverage requirement enforced by Gerrit. Simply add the tag followed by a description to justify -bypassing code coverage. +bypassing code coverage. You must include a reference to a bug (in the form +`b:1234567` or `b/1234567`) that tracks whatever issue is impeding coverage. ``` LOW_COVERAGE_REASON=no emulator for the ANX7483 exists b/248086547 diff --git a/util/check_low_coverage_reason.py b/util/check_low_coverage_reason.py new file mode 100755 index 0000000000..c6119f6a6a --- /dev/null +++ b/util/check_low_coverage_reason.py @@ -0,0 +1,58 @@ +#!/usr/bin/env python3 +# Copyright 2023 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +"""Ensure commit messages using LOW_COVERAGE_REASON include a bug.""" + +import logging +import pathlib +import re +import sys + +from chromite.lib import commandline +from chromite.lib import cros_build_lib +from chromite.lib import git + + +# Look for LOW_COVERAGE_REASON and then an optional b{:|/}number bug reference. +LOW_COV_REGEX = re.compile( + r"\s*(LOW_COVERAGE_REASON=)(?:(?!b[/|:][\d]+).)*(b[/|:]([\d]+))?" +) +EC_BASE = pathlib.Path(__file__).resolve().parent.parent + + +def main(argv=None): + """Check for bug in LOW_COVERAGE_REASON.""" + parser = commandline.ArgumentParser() + parser.add_argument( + "commit_id", + help="Commit whose message will be checked.", + ) + opts = parser.parse_args(argv) + + if opts.commit_id == "pre-submit": + # Only run check if verifying an actual commit. + return 0 + + try: + commit_log = git.Log(EC_BASE, rev=opts.commit_id, max_count=1) + except cros_build_lib.RunCommandError as err: + logging.error("Unable to query git log: %s", str(err)) + return 1 + + # Search commit message for LOW_COVERAGE_REASON and bug + matches = LOW_COV_REGEX.findall(commit_log) + if matches and not any({m[2] for m in matches}): + # We have LOW_COVERAGE_REASON line(s) but none include a bug + logging.error( + "LOW_COVERAGE_REASON line must include one or more bugs " + "tracking the reason for missing coverage" + ) + return 1 + + return 0 + + +if __name__ == "__main__": + sys.exit(main(sys.argv[1:])) -- cgit v1.2.1 From 764c88f6b9a4f2363609a5f5bf0d4ce3dee7250d Mon Sep 17 00:00:00 2001 From: wen zhang Date: Sun, 23 Apr 2023 17:01:52 +0800 Subject: screebo: Implement LED behavior This defines the LED's behavior according to the OEM specification. Check more detail in the bug. BUG=b:278153037 TEST=1.ectool led battery {color} can set the right color 2.led works as intended behavior in different states Change-Id: I42b67170d0d07554626b2a0158cebc8406be60a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4463817 Tested-by: wen zhang Reviewed-by: caveh jalali Commit-Queue: wen zhang Reviewed-by: Mike Lee --- zephyr/program/rex/screebo/led_pins.dtsi | 31 +++++++ zephyr/program/rex/screebo/led_policy.dtsi | 140 +++++++++++++++++++++++++++++ zephyr/program/rex/screebo/project.overlay | 2 + 3 files changed, 173 insertions(+) create mode 100644 zephyr/program/rex/screebo/led_pins.dtsi create mode 100644 zephyr/program/rex/screebo/led_policy.dtsi diff --git a/zephyr/program/rex/screebo/led_pins.dtsi b/zephyr/program/rex/screebo/led_pins.dtsi new file mode 100644 index 0000000000..a71f0562d0 --- /dev/null +++ b/zephyr/program/rex/screebo/led_pins.dtsi @@ -0,0 +1,31 @@ +/* Copyright 2023 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + gpio-led-pins { + compatible = "cros-ec,gpio-led-pins"; + + combo_led: combo-led { + led-id = "EC_LED_ID_BATTERY_LED"; + led-pins = <&gpio_led_1_l &gpio_led_2_l>; + color_off: color-off { + led-color = "LED_OFF"; + led-values = <1 1>; + }; + + color_amber: color-amber { + led-color = "LED_AMBER"; + br-color = "EC_LED_COLOR_AMBER"; + led-values = <1 0>; + }; + + color_white: color-white { + led-color = "LED_WHITE"; + br-color = "EC_LED_COLOR_WHITE"; + led-values = <0 1>; + }; + }; + }; +}; diff --git a/zephyr/program/rex/screebo/led_policy.dtsi b/zephyr/program/rex/screebo/led_policy.dtsi new file mode 100644 index 0000000000..d3e2a53351 --- /dev/null +++ b/zephyr/program/rex/screebo/led_policy.dtsi @@ -0,0 +1,140 @@ +#include + +/ { + led-colors { + compatible = "cros-ec,led-policy"; + + power-state-charge-lvl-1 { + charge-state = "PWR_STATE_CHARGE"; + + /* Battery display percent range (>= Empty, <= 94%) */ + batt-lvl = ; + + color-0 { + led-color = <&color_amber>; + }; + }; + + power-state-charge-lvl-2 { + charge-state = "PWR_STATE_CHARGE"; + + /* Battery display percent range (>= 95) */ + batt-lvl = <95 100>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-near-full { + charge-state = "PWR_STATE_CHARGE_NEAR_FULL"; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery display percent range (>= 11%, <= 100%) */ + batt-lvl = <(BATTERY_LEVEL_LOW + 1) BATTERY_LEVEL_FULL>; + + color-0 { + led-color = <&color_white>; + }; + }; + + power-state-discharge-s0-batt-low { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S0"; + /* Battery display percent range (>= 0, <= 10%) */ + batt-lvl = ; + + /* Amber 1 sec on, 3 sec off */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s3 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S3"; + + /* White 1 sec on, 3 sec off */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-discharge-s5 { + charge-state = "PWR_STATE_DISCHARGE"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-error-s0 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S0"; + /* Amber 1 sec on, 1 sec off */ + color-0 { + led-color = <&color_amber>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <1000>; + }; + }; + + power-state-error-s3 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S3"; + /* White 1 sec on, 3 sec off */ + color-0 { + led-color = <&color_white>; + period-ms = <1000>; + }; + color-1 { + led-color = <&color_off>; + period-ms = <3000>; + }; + }; + + power-state-error-s5 { + charge-state = "PWR_STATE_ERROR"; + chipset-state = "POWER_S5"; + + color-0 { + led-color = <&color_off>; + }; + }; + + power-state-forced-idle { + charge-state = "PWR_STATE_FORCED_IDLE"; + + /* White 2 sec on, Amber 2 sec on */ + color-0 { + led-color = <&color_white>; + period-ms = <2000>; + }; + color-1 { + led-color = <&color_amber>; + period-ms = <2000>; + }; + }; + }; +}; diff --git a/zephyr/program/rex/screebo/project.overlay b/zephyr/program/rex/screebo/project.overlay index 35156be4f4..f1f13d91cb 100644 --- a/zephyr/program/rex/screebo/project.overlay +++ b/zephyr/program/rex/screebo/project.overlay @@ -13,6 +13,8 @@ #include "../usbc.dtsi" /* Screebo project DTS includes */ +#include "led_pins.dtsi" +#include "led_policy.dtsi" #include "temp_sensors.dtsi" / { -- cgit v1.2.1 From b98a347e1b0711a565f94b65beb8a8850169e190 Mon Sep 17 00:00:00 2001 From: Yunlong Jia Date: Tue, 16 May 2023 14:24:02 +0800 Subject: gothrax: Initial Zephyr EC image Create the initial Zephyr EC image for the gothrax variant based on the nereid reference board. (Auto-Generated by create_zephyr_ec_image.sh version 1.0.0). BUG=b:279614675 BRANCH=None TEST=PASS Change-Id: I7a977ed3448101a400a01ae06b452dc8577ebf49 Signed-off-by: Yunlong Jia Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4537641 Reviewed-by: Henry Sun Commit-Queue: Henry Sun --- zephyr/program/nissa/BUILD.py | 3 + zephyr/program/nissa/gothrax/generated.dtsi | 260 +++++++++++++++ zephyr/program/nissa/gothrax/keyboard.dtsi | 48 +++ zephyr/program/nissa/gothrax/motionsense.dtsi | 147 +++++++++ zephyr/program/nissa/gothrax/nereid_vif.xml | 350 ++++++++++++++++++++ zephyr/program/nissa/gothrax/overlay.dtsi | 409 ++++++++++++++++++++++++ zephyr/program/nissa/gothrax/power_signals.dtsi | 223 +++++++++++++ zephyr/program/nissa/gothrax/project.conf | 24 ++ zephyr/program/nissa/gothrax/project.overlay | 14 + zephyr/program/nissa/gothrax/pwm_leds.dtsi | 60 ++++ zephyr/program/nissa/gothrax/src/charger.c | 55 ++++ zephyr/program/nissa/gothrax/src/hdmi.c | 29 ++ zephyr/program/nissa/gothrax/src/keyboard.c | 29 ++ zephyr/program/nissa/gothrax/src/usbc.c | 329 +++++++++++++++++++ 14 files changed, 1980 insertions(+) create mode 100644 zephyr/program/nissa/gothrax/generated.dtsi create mode 100644 zephyr/program/nissa/gothrax/keyboard.dtsi create mode 100644 zephyr/program/nissa/gothrax/motionsense.dtsi create mode 100644 zephyr/program/nissa/gothrax/nereid_vif.xml create mode 100644 zephyr/program/nissa/gothrax/overlay.dtsi create mode 100644 zephyr/program/nissa/gothrax/power_signals.dtsi create mode 100644 zephyr/program/nissa/gothrax/project.conf create mode 100644 zephyr/program/nissa/gothrax/project.overlay create mode 100644 zephyr/program/nissa/gothrax/pwm_leds.dtsi create mode 100644 zephyr/program/nissa/gothrax/src/charger.c create mode 100644 zephyr/program/nissa/gothrax/src/hdmi.c create mode 100644 zephyr/program/nissa/gothrax/src/keyboard.c create mode 100644 zephyr/program/nissa/gothrax/src/usbc.c diff --git a/zephyr/program/nissa/BUILD.py b/zephyr/program/nissa/BUILD.py index 0a10912552..04b1f62778 100644 --- a/zephyr/program/nissa/BUILD.py +++ b/zephyr/program/nissa/BUILD.py @@ -113,3 +113,6 @@ uldren = register_nissa_project( project_name="uldren", chip="npcx9m3f", ) +gothrax = register_nereid_project( + project_name="gothrax", +) diff --git a/zephyr/program/nissa/gothrax/generated.dtsi b/zephyr/program/nissa/gothrax/generated.dtsi new file mode 100644 index 0000000000..bca58c478e --- /dev/null +++ b/zephyr/program/nissa/gothrax/generated.dtsi @@ -0,0 +1,260 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * This file is auto-generated - do not edit! + */ + +/ { + + named-adc-channels { + compatible = "named-adc-channels"; + + adc_ec_vsense_pp1050_proc: ec_vsense_pp1050_proc { + enum-name = "ADC_PP1050_PROC"; + io-channels = <&adc0 14>; + }; + adc_ec_vsense_pp3300_s5: ec_vsense_pp3300_s5 { + enum-name = "ADC_PP3300_S5"; + io-channels = <&adc0 0>; + }; + adc_temp_sensor_1: temp_sensor_1 { + enum-name = "ADC_TEMP_SENSOR_1"; + io-channels = <&adc0 2>; + }; + adc_temp_sensor_2: temp_sensor_2 { + enum-name = "ADC_TEMP_SENSOR_2"; + io-channels = <&adc0 3>; + }; + adc_temp_sensor_3: temp_sensor_3 { + enum-name = "ADC_TEMP_SENSOR_3"; + io-channels = <&adc0 13>; + }; + }; + + named-gpios { + compatible = "named-gpios"; + + gpio_acc_int_l: acc_int_l { + gpios = <&gpioc 0 GPIO_INPUT>; + }; + gpio_all_sys_pwrgd: all_sys_pwrgd { + gpios = <&gpiob 7 GPIO_INPUT>; + }; + gpio_ccd_mode_odl: ccd_mode_odl { + gpios = <&gpioh 5 GPIO_INPUT>; + enum-name = "GPIO_CCD_MODE_ODL"; + }; + gpio_cpu_c10_gate_l: cpu_c10_gate_l { + gpios = <&gpiog 1 GPIO_INPUT>; + }; + gpio_ec_battery_pres_odl: ec_battery_pres_odl { + gpios = <&gpioi 4 GPIO_INPUT>; + enum-name = "GPIO_BATT_PRES_ODL"; + }; + gpio_ec_cbi_wp: ec_cbi_wp { + gpios = <&gpioj 5 GPIO_OUTPUT>; + }; + gpio_ec_edp_bl_en_od: ec_edp_bl_en_od { + gpios = <&gpiok 4 GPIO_ODR_HIGH>; + enum-name = "GPIO_ENABLE_BACKLIGHT"; + }; + gpio_ec_entering_rw: ec_entering_rw { + gpios = <&gpioc 7 GPIO_OUTPUT>; + enum-name = "GPIO_ENTERING_RW"; + }; + gpio_ec_gsc_packet_mode: ec_gsc_packet_mode { + gpios = <&gpioh 1 GPIO_OUTPUT>; + enum-name = "GPIO_PACKET_MODE_EN"; + }; + gpio_ec_pch_wake_odl: ec_pch_wake_odl { + gpios = <&gpiob 2 GPIO_ODR_LOW>; + }; + gpio_ec_prochot_odl: ec_prochot_odl { + gpios = <&gpioi 1 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_dsw_pwrok: ec_soc_dsw_pwrok { + gpios = <&gpiol 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_hdmi_hpd: ec_soc_hdmi_hpd { + gpios = <&gpiok 7 GPIO_OUTPUT>; + }; + gpio_ec_soc_int_odl: ec_soc_int_odl { + gpios = <&gpiod 5 GPIO_ODR_HIGH>; + enum-name = "GPIO_EC_INT_L"; + }; + gpio_ec_soc_pch_pwrok_od: ec_soc_pch_pwrok_od { + gpios = <&gpiod 6 GPIO_ODR_HIGH>; + }; + gpio_ec_soc_pwr_btn_odl: ec_soc_pwr_btn_odl { + gpios = <&gpiob 6 GPIO_ODR_HIGH>; + enum-name = "GPIO_PCH_PWRBTN_L"; + }; + gpio_ec_soc_rsmrst_l: ec_soc_rsmrst_l { + gpios = <&gpioh 0 GPIO_OUTPUT>; + }; + gpio_ec_soc_rtcrst: ec_soc_rtcrst { + gpios = <&gpiok 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_sys_pwrok: ec_soc_sys_pwrok { + gpios = <&gpiof 2 GPIO_OUTPUT>; + }; + gpio_ec_soc_vccst_pwrgd_od: ec_soc_vccst_pwrgd_od { + gpios = <&gpioe 5 GPIO_ODR_HIGH>; + }; + gpio_ec_wp_odl: ec_wp_odl { + gpios = <&gpioa 6 (GPIO_INPUT | GPIO_ACTIVE_LOW)>; + }; + gpio_en_kb_bl: en_kb_bl { + gpios = <&gpioj 3 GPIO_OUTPUT>; + enum-name = "GPIO_EN_KEYBOARD_BACKLIGHT"; + }; + gpio_en_pp3300_s5: en_pp3300_s5 { + gpios = <&gpioc 5 GPIO_OUTPUT>; + enum-name = "GPIO_TEMP_SENSOR_POWER"; + }; + gpio_en_pp5000_pen_x: en_pp5000_pen_x { + gpios = <&gpiob 5 GPIO_OUTPUT>; + }; + gpio_en_pp5000_s5: en_pp5000_s5 { + gpios = <&gpiok 5 GPIO_OUTPUT>; + }; + gpio_en_slp_z: en_slp_z { + gpios = <&gpiok 3 GPIO_OUTPUT>; + }; + gpio_en_usb_a0_vbus: en_usb_a0_vbus { + gpios = <&gpiol 6 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc1_vconn: en_usb_c0_cc1_vconn { + gpios = <&gpioh 4 GPIO_OUTPUT>; + }; + gpio_en_usb_c0_cc2_vconn: en_usb_c0_cc2_vconn { + gpios = <&gpioh 6 GPIO_OUTPUT>; + }; + gpio_gsc_ec_pwr_btn_odl: gsc_ec_pwr_btn_odl { + gpios = <&gpioe 2 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_POWER_BUTTON_L"; + }; + gpio_hdmi_sel: hdmi_sel { + gpios = <&gpioc 6 GPIO_OUTPUT>; + }; + gpio_imu_int_l: imu_int_l { + gpios = <&gpioj 0 GPIO_INPUT>; + }; + gpio_imvp91_vrrdy_od: imvp91_vrrdy_od { + gpios = <&gpioj 4 GPIO_INPUT>; + }; + gpio_lid_open: lid_open { + gpios = <&gpiof 3 GPIO_INPUT>; + enum-name = "GPIO_LID_OPEN"; + }; + gpio_pen_detect_odl: pen_detect_odl { + gpios = <&gpioj 1 GPIO_INPUT_PULL_UP>; + }; + gpio_pg_pp1050_mem_s3_od: pg_pp1050_mem_s3_od { + gpios = <&gpiod 3 GPIO_INPUT>; + }; + gpio_pg_pp5000_s5_od: pg_pp5000_s5_od { + gpios = <&gpioe 3 GPIO_INPUT>; + }; + gpio_rsmrst_pwrgd_l: rsmrst_pwrgd_l { + gpios = <&gpioe 1 GPIO_INPUT_PULL_UP>; + }; + gpio_slp_s0_l: slp_s0_l { + gpios = <&gpioe 4 GPIO_INPUT>; + }; + gpio_slp_s3_l: slp_s3_l { + gpios = <&gpioh 3 GPIO_INPUT>; + }; + gpio_slp_s4_l: slp_s4_l { + gpios = <&gpioi 5 GPIO_INPUT>; + }; + gpio_slp_sus_l: slp_sus_l { + gpios = <&gpiog 2 GPIO_INPUT>; + }; + gpio_sub_usb_a1_ilimit_sdp: sub_usb_a1_ilimit_sdp { + gpios = <&gpiof 1 GPIO_OUTPUT>; + enum-name = "GPIO_USB2_ILIM_SEL"; + }; + gpio_sys_rst_odl: sys_rst_odl { + gpios = <&gpiod 1 GPIO_ODR_HIGH>; + }; + gpio_tablet_mode_l: tablet_mode_l { + gpios = <&gpioa 7 GPIO_INPUT>; + enum-name = "GPIO_TABLET_MODE_L"; + }; + gpio_usb_a0_ilimit_sdp: usb_a0_ilimit_sdp { + gpios = <&gpiol 5 GPIO_OUTPUT>; + enum-name = "GPIO_USB1_ILIM_SEL"; + }; + gpio_usb_c0_frs: usb_c0_frs { + gpios = <&gpioc 4 GPIO_OUTPUT>; + }; + gpio_usb_c0_int_odl: usb_c0_int_odl { + gpios = <&gpiok 0 GPIO_INPUT_PULL_UP>; + }; + gpio_vccin_aux_vid0: vccin_aux_vid0 { + gpios = <&gpiod 0 GPIO_INPUT>; + }; + gpio_vccin_aux_vid1: vccin_aux_vid1 { + gpios = <&gpiok 1 GPIO_INPUT>; + }; + gpio_voldn_btn_odl: voldn_btn_odl { + gpios = <&gpioi 6 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_DOWN_L"; + }; + gpio_volup_btn_odl: volup_btn_odl { + gpios = <&gpioi 7 GPIO_INPUT_PULL_UP>; + enum-name = "GPIO_VOLUME_UP_L"; + }; + }; + + named-i2c-ports { + compatible = "named-i2c-ports"; + + i2c_ec_i2c_eeprom: ec_i2c_eeprom { + i2c-port = <&i2c0>; + enum-names = "I2C_PORT_EEPROM"; + }; + i2c_ec_i2c_batt: ec_i2c_batt { + i2c-port = <&i2c1>; + enum-names = "I2C_PORT_BATTERY"; + }; + i2c_ec_i2c_sensor: ec_i2c_sensor { + i2c-port = <&i2c2>; + enum-names = "I2C_PORT_SENSOR"; + }; + i2c_ec_i2c_sub_usb_c1: ec_i2c_sub_usb_c1 { + i2c-port = <&i2c4>; + enum-names = "I2C_PORT_USB_C1_TCPC"; + }; + i2c_ec_i2c_usb_c0: ec_i2c_usb_c0 { + i2c-port = <&i2c5>; + enum-names = "I2C_PORT_USB_C0_TCPC"; + }; + }; +}; + +&adc0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; diff --git a/zephyr/program/nissa/gothrax/keyboard.dtsi b/zephyr/program/nissa/gothrax/keyboard.dtsi new file mode 100644 index 0000000000..1742e1a50f --- /dev/null +++ b/zephyr/program/nissa/gothrax/keyboard.dtsi @@ -0,0 +1,48 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + kblight { + compatible = "cros-ec,kblight-pwm"; + /* + * Use 324 Hz so that 32Khz clock source is used, + * which is not gated in power saving mode. + */ + pwms = <&pwm0 0 PWM_HZ(324) PWM_POLARITY_NORMAL>; + }; +}; + +&pwm0 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm0_gpa0_default>; + pinctrl-names = "default"; +}; + +&cros_kb_raw { + status = "okay"; + /* No KSO2 (it's inverted and implemented by GPIO) */ + pinctrl-0 = <&ksi0_default + &ksi1_default + &ksi2_default + &ksi3_default + &ksi4_default + &ksi5_default + &ksi6_default + &ksi7_default + &kso0_default + &kso1_default + &kso3_default + &kso4_default + &kso5_default + &kso6_default + &kso7_default + &kso8_default + &kso9_default + &kso10_default + &kso11_default + &kso12_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/program/nissa/gothrax/motionsense.dtsi b/zephyr/program/nissa/gothrax/motionsense.dtsi new file mode 100644 index 0000000000..a65bb48fbd --- /dev/null +++ b/zephyr/program/nissa/gothrax/motionsense.dtsi @@ -0,0 +1,147 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include + + +/ { + aliases { + /* + * Interrupt bindings for sensor devices. + */ + bmi3xx-int = &base_accel; + bma4xx-int = &lid_accel; + }; + + /* + * Declare mutexes used by sensor drivers. + * A mutex node is used to create an instance of mutex_t. + * A mutex node is referenced by a sensor node if the + * corresponding sensor driver needs to use the + * instance of the mutex. + */ + motionsense-mutex { + compatible = "cros-ec,motionsense-mutex"; + lid_mutex: lid-mutex { + }; + + base_mutex: base-mutex { + }; + }; + + /* Rotation matrix used by drivers. */ + motionsense-rotation-ref { + compatible = "cros-ec,motionsense-rotation-ref"; + lid_rot_ref: lid-rotation-ref { + mat33 = <0 (-1) 0 + (-1) 0 0 + 0 0 (-1)>; + }; + + base_rot_ref: base-rotation-ref { + mat33 = <0 1 0 + (-1) 0 0 + 0 0 1>; + }; + }; + + /* + * Driver specific data. A driver-specific data can be shared with + * different motion sensors while they are using the same driver. + * + * If a node's compatible starts with "cros-ec,accelgyro-", it is for + * a common structure defined in accelgyro.h. + * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for + * "struct als_drv_data_t" in accelgyro.h + */ + motionsense-sensor-data { + bmi323_data: bmi323-drv-data { + compatible = "cros-ec,drvdata-bmi3xx"; + status = "okay"; + }; + + bma422_data: bma422-drv-data { + compatible = "cros-ec,drvdata-bma4xx"; + status = "okay"; + }; + }; + + /* + * List of motion sensors that creates motion_sensors array. + * The nodelabel "lid_accel" and "base_accel" are used to indicate + * motion sensor IDs for lid angle calculation. + * TODO(b/238139272): The first entries of the array must be + * accelerometers,then gyroscope. Fix this dependency in the DTS + * processing which makes the devicetree entries independent. + */ + motionsense-sensor { + lid_accel: lid-accel { + compatible = "cros-ec,bma4xx"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_LID"; + mutex = <&lid_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&lid_rot_ref>; + default-range = <2>; + drv-data = <&bma422_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_accel: base-accel { + compatible = "cros-ec,bmi3xx-accel"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + configs { + compatible = + "cros-ec,motionsense-sensor-config"; + ec-s0 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + ec-s3 { + odr = <(10000 | ROUND_UP_FLAG)>; + }; + }; + }; + + base_gyro: base-gyro { + compatible = "cros-ec,bmi3xx-gyro"; + status = "okay"; + + active-mask = "SENSOR_ACTIVE_S0_S3"; + location = "MOTIONSENSE_LOC_BASE"; + mutex = <&base_mutex>; + port = <&i2c_ec_i2c_sensor>; + rot-standard-ref = <&base_rot_ref>; + drv-data = <&bmi323_data>; + }; + }; + + motionsense-sensor-info { + compatible = "cros-ec,motionsense-sensor-info"; + + /* + * list of GPIO interrupts that have to + * be enabled at initial stage + */ + sensor-irqs = <&int_imu &int_lid_imu>; + }; +}; diff --git a/zephyr/program/nissa/gothrax/nereid_vif.xml b/zephyr/program/nissa/gothrax/nereid_vif.xml new file mode 100644 index 0000000000..91c8dbe68b --- /dev/null +++ b/zephyr/program/nissa/gothrax/nereid_vif.xml @@ -0,0 +1,350 @@ + + + 3.19 + + USB-IF + VIF Editor + 3.2.4.0 + + Google + Nereid + 1 + 0 + Port Product + Reference Platform + + + + + + + + + 0 + Type-C® + + + DRP + DRP + + Charging Port + + + + + + + + + Revision 3 + + + + + + + 18D1 + 505A + + + + + + + USB Type-C® Receptacle + + + + + + + + + + + + No Interruption Possible + + + + + + + + + + + + + + 1.5A + + Both + + + + + + + 15000 mW + Assured + + + + + USB 3.2 Gen 1x1 + + + + + + + + + CDP + + + + 15000 mW + + + + FR_Swap not supported + + + + Over-Current Response + + + + + Fixed + 100% IOC + 5000 mV + 3000 mA + 0 msec + 3000 mA + + + + + + 45000 mW + + + + + FR_Swap not supported + + + + + + Fixed + 5000 mV + 3000 mA + + + + Battery + 15000 mW + 4750 mV + 15000 mV + + + + Variable + 4750 mV + 15000 mV + 3000 mA + + + + + + + + + + + + + + + + + Undefined + PDUSB Host + + + 18D1 + 505A + 0000 + + + + + + + 1 + Type-C® + + + DRP + DRP + + Charging Port + + + + + + + + + Revision 3 + + + + + + + 18D1 + 505A + + + + + + + USB Type-C® Receptacle + + + + + + + + + + + + No Interruption Possible + + + + + + + + + + + + + + 1.5A + + Both + + + + + + + 15000 mW + Assured + + + + + USB 3.2 Gen 1x1 + + + + + + + + + CDP + + + + 15000 mW + + + + FR_Swap not supported + + + + Over-Current Response + + + + + Fixed + 100% IOC + 5000 mV + 3000 mA + 0 msec + 3000 mA + + + + + + 45000 mW + + + + + FR_Swap not supported + + + + + + Fixed + 5000 mV + 3000 mA + + + + Battery + 15000 mW + 4750 mV + 15000 mV + + + + Variable + 4750 mV + 15000 mV + 3000 mA + + + + + + + + + + + + + + + + + Undefined + PDUSB Host + + + 18D1 + 505A + 0000 + + \ No newline at end of file diff --git a/zephyr/program/nissa/gothrax/overlay.dtsi b/zephyr/program/nissa/gothrax/overlay.dtsi new file mode 100644 index 0000000000..36d30a0fce --- /dev/null +++ b/zephyr/program/nissa/gothrax/overlay.dtsi @@ -0,0 +1,409 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include +#include + +/ { + aliases { + gpio-cbi-wp = &gpio_ec_cbi_wp; + gpio-wp = &gpio_ec_wp_odl; + int-wp = &int_wp_l; + /* + * USB-C: interrupt input. + * I2C pins are on i2c_ec_i2c_sub_usb_c1 + */ + gpio-usb-c1-int-odl = &gpio_sb_1; + /* + * USB-A: VBUS enable output + * LTE: power enable output + */ + gpio-en-usb-a1-vbus = &gpio_sb_2; + /* + * HDMI: power enable output, HDMI enable output, + * and HPD input + */ + gpio-en-rails-odl = &gpio_sb_1; + gpio-hdmi-en-odl = &gpio_sb_4; + gpio-hpd-odl = &gpio_sb_3; + /* + * Enable S5 rails for LTE sub-board + */ + gpio-en-sub-s5-rails = &gpio_sb_2; + }; + + + ec-console { + compatible = "ec-console"; + disabled = "events", "lpc", "hostcmd"; + }; + + batteries { + default_battery: smp { + compatible = "smp,l20m3pg0", "battery-smart"; + }; + }; + + hibernate-wake-pins { + compatible = "cros-ec,hibernate-wake-pins"; + wakeup-irqs = < + &int_power_button + &int_lid_open + >; + }; + + gpio-interrupts { + compatible = "cros-ec,gpio-interrupts"; + + int_power_button: power_button { + irq-pin = <&gpio_gsc_ec_pwr_btn_odl>; + flags = ; + handler = "power_button_interrupt"; + }; + int_vol_down: vol_down { + irq-pin = <&gpio_voldn_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_vol_up: vol_up { + irq-pin = <&gpio_volup_btn_odl>; + flags = ; + handler = "button_interrupt"; + }; + int_wp_l: wp_l { + irq-pin = <&gpio_ec_wp_odl>; + flags = ; + handler = "switch_interrupt"; + }; + int_lid_open: lid_open { + irq-pin = <&gpio_lid_open>; + flags = ; + handler = "lid_interrupt"; + }; + int_tablet_mode: tablet_mode { + irq-pin = <&gpio_tablet_mode_l>; + flags = ; + handler = "gmr_tablet_switch_isr"; + }; + int_imu: ec_imu { + irq-pin = <&gpio_imu_int_l>; + flags = ; + handler = "bmi3xx_interrupt"; + }; + int_lid_imu: lid_imu { + irq-pin = <&gpio_acc_int_l>; + flags = ; + handler = "bma4xx_interrupt"; + }; + int_usb_c0: usb_c0 { + irq-pin = <&gpio_usb_c0_int_odl>; + flags = ; + handler = "usb_c0_interrupt"; + }; + int_usb_c1: usb_c1 { + irq-pin = <&gpio_sb_1>; + flags = ; + handler = "usb_c1_interrupt"; + }; + }; + + unused-pins { + compatible = "unused-gpios"; + unused-gpios = <&gpioc 3 0>, + <&gpiod 4 0>, + <&gpiod 7 0>, + <&gpioh 2 0>, + <&gpioj 7 0>, + <&gpiol 4 0>; + }; + + named-gpios { + /* + * EC doesn't take any specific action on CC/SBU disconnect due to + * fault, but this definition is useful for hardware testing. + */ + gpio_usb_c0_prot_fault_odl: usb_c0_prot_fault_odl { + gpios = <&gpiok 6 GPIO_INPUT_PULL_UP>; + }; + + gpio_sb_1: sb_1 { + gpios = <&gpioe 6 0>; + no-auto-init; + }; + gpio_sb_2: sb_2 { + gpios = <&gpiof 0 0>; + no-auto-init; + }; + + gpio_sb_3: sb_3 { + gpios = <&gpioe 7 0>; + no-auto-init; + }; + gpio_sb_4: sb_4 { + gpios = <&gpioe 0 0>; + no-auto-init; + }; + }; + + temp_memory: memory { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_1>; + }; + temp_charger: charger { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_2>; + }; + temp_ambient: ambient { + compatible = "cros-ec,temp-sensor-thermistor"; + thermistor = <&thermistor_3V3_51K1_47K_4050B>; + adc = <&adc_temp_sensor_3>; + }; + + named-temp-sensors { + compatible = "cros-ec,temp-sensors"; + memory { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_memory>; + }; + charger { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_charger>; + }; + ambient { + temp_fan_off = <35>; + temp_fan_max = <60>; + temp_host_high = <85>; + temp_host_halt = <90>; + temp_host_release_high = <80>; + power-good-pin = <&gpio_ec_soc_dsw_pwrok>; + sensor = <&temp_ambient>; + }; + }; + + usba { + compatible = "cros-ec,usba-port-enable-pins"; + /* + * sb_2 is only configured as GPIO when USB-A1 is present, + * but it's still safe to control when disabled. + * + * ILIM_SEL pins are referred to by legacy enum name, + * GPIO_USB*_ILIM_SEL. The one for port A1 is unused on + * sub-boards that don't have USB-A so is safe to control + * regardless of system configuration. + */ + enable-pins = <&gpio_en_usb_a0_vbus &gpio_sb_2>; + status = "okay"; + }; + + usbc { + #address-cells = <1>; + #size-cells = <0>; + + port0@0 { + compatible = "named-usbc-port"; + reg = <0>; + bc12 = <&bc12_port0>; + chg = <&chg_port0>; + tcpc = <&usbpd0>; + usb-mux-chain-0 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_0>; + }; + }; + port0-muxes { + virtual_mux_0: virtual-mux-0 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + }; + port1@1 { + compatible = "named-usbc-port"; + reg = <1>; + bc12 = <&bc12_port1>; + chg = <&chg_port1>; + tcpc = <&tcpc_port1>; + usb-mux-chain-1 { + compatible = "cros-ec,usb-mux-chain"; + usb-muxes = <&virtual_mux_1 &tcpci_mux_1>; + }; + usb_mux_chain_1_no_mux: usb-mux-chain-1-no-mux { + compatible = "cros-ec,usb-mux-chain"; + alternative-chain; + usb-muxes = <&virtual_mux_1>; + }; + }; + port1-muxes { + virtual_mux_1: virtual-mux-1 { + compatible = "cros-ec,usbc-mux-virtual"; + }; + tcpci_mux_1: tcpci-mux-1 { + compatible = "parade,usbc-mux-ps8xxx"; + }; + }; + }; +}; + +&gpio_acc_int_l { + gpios = <&gpioc 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_imu_int_l { + gpios = <&gpioj 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid0 { + gpios = <&gpiod 0 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; +&gpio_vccin_aux_vid1 { + gpios = <&gpiok 1 (GPIO_INPUT | GPIO_VOLTAGE_1P8)>; +}; + +&gpio_ec_prochot_odl { + gpios = <&gpioi 1 (GPIO_ODR_HIGH | GPIO_VOLTAGE_1P8)>; +}; + +&thermistor_3V3_51K1_47K_4050B { + status = "okay"; +}; + +&adc_ec_vsense_pp3300_s5 { + /* + * Voltage divider on input has 47k upper and 220k lower legs with 3 V + * full-scale reading on the ADC. Apply the largest possible multiplier + * (without overflowing int32) to get the best possible approximation + * of the actual ratio, but derate by a factor of two to ensure + * unexpectedly high values won't overflow. + */ + mul = <(715828 / 2)>; + div = <(589820 / 2)>; +}; + +&adc0 { + pinctrl-0 = <&adc0_ch0_gpi0_default + &adc0_ch2_gpi2_default + &adc0_ch3_gpi3_default + &adc0_ch13_gpl0_default + &adc0_ch14_gpl1_default>; + pinctrl-names = "default"; +}; + +&pinctrl { + i2c4_clk_gpe0_sleep: i2c4_clk_gpe0_sleep { + pinmuxs = <&pinctrle 0 IT8XXX2_ALT_DEFAULT>; + }; + i2c4_data_gpe7_sleep: i2c4_data_gpe7_sleep { + pinmuxs = <&pinctrle 7 IT8XXX2_ALT_DEFAULT>; + }; + i2c2_clk_gpf6_default: i2c2_clk_gpf6_default { + gpio-voltage = "1v8"; + }; + i2c2_data_gpf7_default: i2c2_data_gpf7_default { + gpio-voltage = "1v8"; + }; +}; + +&i2c0 { + label = "I2C_EEPROM"; + clock-frequency = ; + + cbi_eeprom: eeprom@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <2048>; + pagesize = <16>; + address-width = <8>; + timeout = <5>; + }; + pinctrl-0 = <&i2c0_clk_gpb3_default + &i2c0_data_gpb4_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + label = "I2C_BATTERY"; + clock-frequency = <50000>; + pinctrl-0 = <&i2c1_clk_gpc1_default + &i2c1_data_gpc2_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + label = "I2C_SENSOR"; + clock-frequency = ; + pinctrl-0 = <&i2c2_clk_gpf6_default + &i2c2_data_gpf7_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + label = "I2C_SUB_C1_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c4_clk_gpe0_default + &i2c4_data_gpe7_default>; + pinctrl-1 = <&i2c4_clk_gpe0_sleep + &i2c4_data_gpe7_sleep>; + pinctrl-names = "default", "sleep"; + + bc12_port1: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port1: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; + + tcpc_port1: ps8745@b { + compatible = "parade,ps8xxx"; + reg = <0xb>; + tcpc-flags = <(TCPC_FLAGS_TCPCI_REV2_0)>; + }; +}; + +&i2c_ec_i2c_sub_usb_c1 { + /* + * Dynamic speed setting is used for AP-controlled firmware update + * of PS8745 TCPC/redriver: the AP lowers speed to 400 kHz in order + * to use more efficient window programming, then sets it back when + * done. + */ + dynamic-speed; +}; + +&i2c5 { + label = "I2C_USB_C0_TCPC"; + clock-frequency = ; + pinctrl-0 = <&i2c5_clk_gpa4_default + &i2c5_data_gpa5_default>; + pinctrl-names = "default"; + + bc12_port0: pi3usb9201@5f { + compatible = "pericom,pi3usb9201"; + status = "okay"; + reg = <0x5f>; + }; + + chg_port0: sm5803@32 { + compatible = "siliconmitus,sm5803"; + status = "okay"; + reg = <0x32>; + }; +}; + +&usbpd0 { + status = "okay"; +}; diff --git a/zephyr/program/nissa/gothrax/power_signals.dtsi b/zephyr/program/nissa/gothrax/power_signals.dtsi new file mode 100644 index 0000000000..8affae03b1 --- /dev/null +++ b/zephyr/program/nissa/gothrax/power_signals.dtsi @@ -0,0 +1,223 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + chosen { + intel-ap-pwrseq,espi = &espi0; + }; + + common-pwrseq { + compatible = "intel,ap-pwrseq"; + + sys-pwrok-delay = <10>; + all-sys-pwrgd-timeout = <20>; + }; + + pwr-en-pp5000-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP5000_S5 enable output to regulator"; + enum-name = "PWR_EN_PP5000_A"; + gpios = <&gpiok 5 0>; + output; + }; + pwr-en-pp3300-s5 { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PP3300_S5 enable output to LS"; + enum-name = "PWR_EN_PP3300_A"; + gpios = <&gpioc 5 0>; + output; + }; + pwr-pg-ec-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST power good from regulator"; + enum-name = "PWR_RSMRST"; + gpios = <&gpioe 1 0>; + interrupt-flags = ; + }; + pwr-ec-pch-rsmrst-odl { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "RSMRST output to PCH"; + enum-name = "PWR_EC_PCH_RSMRST"; + gpios = <&gpioh 0 0>; + output; + }; + pwr-slp-s0-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S0_L input from PCH"; + enum-name = "PWR_SLP_S0"; + gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-s3-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_S3_L input from PCH"; + enum-name = "PWR_SLP_S3"; + gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-slp-sus-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SLP_SUS_L input from PCH"; + enum-name = "PWR_SLP_SUS"; + gpios = <&gpiog 2 GPIO_ACTIVE_LOW>; + interrupt-flags = ; + }; + pwr-ec-soc-dsw-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "DSW_PWROK output to PCH"; + enum-name = "PWR_EC_SOC_DSW_PWROK"; + gpios = <&gpiol 7 0>; + output; + }; + pwr-vccst-pwrgd-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VCCST_PWRGD output to PCH"; + enum-name = "PWR_VCCST_PWRGD"; + gpios = <&gpioe 5 (GPIO_OPEN_DRAIN | GPIO_VOLTAGE_1P8)>; + output; + }; + pwr-imvp9-vrrdy-od { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "VRRDY input from IMVP9"; + enum-name = "PWR_IMVP9_VRRDY"; + gpios = <&gpioj 4 0>; + }; + pwr-pch-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "PCH_PWROK output to PCH"; + enum-name = "PWR_PCH_PWROK"; + gpios = <&gpiod 6 GPIO_OPEN_DRAIN>; + output; + }; + pwr-ec-pch-sys-pwrok { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_PWROK output to PCH"; + enum-name = "PWR_EC_PCH_SYS_PWROK"; + gpios = <&gpiof 2 0>; + output; + }; + pwr-sys-rst-l { + compatible = "intel,ap-pwrseq-gpio"; + dbg-label = "SYS_RESET# output to PCH"; + enum-name = "PWR_SYS_RST"; + gpios = <&gpiod 1 (GPIO_ACTIVE_LOW|GPIO_OPEN_DRAIN)>; + output; + }; + pwr-slp-s4 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S4 virtual wire input from PCH"; + enum-name = "PWR_SLP_S4"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S4"; + vw-invert; + }; + pwr-slp-s5 { + compatible = "intel,ap-pwrseq-vw"; + dbg-label = "SLP_S5 virtual wire input from PCH"; + enum-name = "PWR_SLP_S5"; + virtual-wire = "ESPI_VWIRE_SIGNAL_SLP_S5"; + vw-invert; + }; + pwr-all-sys-pwrgd { + /* + * This is a board level signal, since this + * signal needs some special processing. + */ + compatible = "intel,ap-pwrseq-external"; + dbg-label = "Combined all power good"; + enum-name = "PWR_ALL_SYS_PWRGD"; + }; + pwr-adc-pp3300 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP3300_PROC"; + enum-name = "PWR_DSW_PWROK"; + trigger-high = <&vcmp0>; + trigger-low = <&vcmp1>; + }; + pwr-adc-pp1p05 { + compatible = "intel,ap-pwrseq-adc"; + dbg-label = "PP1P05_PROC"; + enum-name = "PWR_PG_PP1P05"; + trigger-high = <&vcmp2>; + trigger-low = <&vcmp3>; + }; + +}; + +/* + * Because the power signals directly reference the GPIOs, + * the correspinding named-gpios need to have no-auto-init set. + */ +&gpio_ec_soc_dsw_pwrok { + no-auto-init; +}; +&gpio_ec_soc_pch_pwrok_od { + no-auto-init; +}; +&gpio_ec_soc_rsmrst_l { + no-auto-init; +}; +&gpio_ec_soc_sys_pwrok { + no-auto-init; +}; +&gpio_ec_soc_vccst_pwrgd_od { + no-auto-init; +}; +&gpio_en_pp3300_s5 { + no-auto-init; +}; +&gpio_en_pp5000_s5 { + no-auto-init; +}; +&gpio_imvp91_vrrdy_od { + no-auto-init; +}; +&gpio_rsmrst_pwrgd_l { + no-auto-init; +}; +&gpio_slp_s0_l { + no-auto-init; +}; +&gpio_slp_s3_l { + no-auto-init; +}; +&gpio_slp_sus_l { + no-auto-init; +}; +&gpio_sys_rst_odl { + no-auto-init; +}; +&vcmp0 { + status = "okay"; + scan-period = ; + comparison = ; + /* + * This is 90% of nominal voltage considering voltage + * divider on ADC input. + */ + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp1 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <2448>; + io-channels = <&adc0 0>; +}; +&vcmp2 { + status = "okay"; + scan-period = ; + comparison = ; + /* Setting at 90% of nominal voltage */ + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; +&vcmp3 { + status = "okay"; + scan-period = ; + comparison = ; + threshold-mv = <945>; + io-channels = <&adc0 14>; +}; diff --git a/zephyr/program/nissa/gothrax/project.conf b/zephyr/program/nissa/gothrax/project.conf new file mode 100644 index 0000000000..ff87f6e591 --- /dev/null +++ b/zephyr/program/nissa/gothrax/project.conf @@ -0,0 +1,24 @@ +# Copyright 2021 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +CONFIG_BOARD_NEREID=y + +# Ensure recovery key combination (esc+refresh+power) is reliable: b/236580049 +CONFIG_PLATFORM_EC_KEYBOARD_PWRBTN_ASSERTS_KSI2=y + +# Sensor drivers +CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y +CONFIG_PLATFORM_EC_ACCELGYRO_BMI3XX=y +CONFIG_PLATFORM_EC_ACCEL_BMA4XX=y +CONFIG_PLATFORM_EC_MAX_SENSOR_FREQ_MILLIHZ=100000 + +# No fan supported, and tach is default-enabled +CONFIG_TACH_IT8XXX2=n + +# Both ports use a PI5USB2546 smart switch with CTL1..3 fixed high, +# for SDP2 or CDP only. +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_CDP_SDP_ONLY=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_DEFAULT_CDP=y +CONFIG_PLATFORM_EC_USB_PORT_POWER_SMART_INVERTED=y diff --git a/zephyr/program/nissa/gothrax/project.overlay b/zephyr/program/nissa/gothrax/project.overlay new file mode 100644 index 0000000000..ee367b9c28 --- /dev/null +++ b/zephyr/program/nissa/gothrax/project.overlay @@ -0,0 +1,14 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "../cbi.dtsi" +#include "../shi.dtsi" + +#include "generated.dtsi" +#include "keyboard.dtsi" +#include "motionsense.dtsi" +#include "overlay.dtsi" +#include "power_signals.dtsi" +#include "pwm_leds.dtsi" diff --git a/zephyr/program/nissa/gothrax/pwm_leds.dtsi b/zephyr/program/nissa/gothrax/pwm_leds.dtsi new file mode 100644 index 0000000000..aa4a76b271 --- /dev/null +++ b/zephyr/program/nissa/gothrax/pwm_leds.dtsi @@ -0,0 +1,60 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm1 1 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm2 2 PWM_HZ(1296) PWM_POLARITY_INVERTED>, + <&pwm3 3 PWM_HZ(1296) PWM_POLARITY_INVERTED>; + }; + }; + + cros-pwmleds { + compatible = "cros-ec,pwm-leds"; + + leds = <&pwm_led0>; + + /**/ + color-map-red = <100 0 0>; + color-map-green = < 0 100 0>; + color-map-blue = < 0 0 100>; + color-map-yellow = < 0 50 50>; + color-map-white = <100 100 100>; + color-map-amber = <100 15 0>; + + brightness-range = <100 100 100 0 0 0>; + + #address-cells = <1>; + #size-cells = <0>; + + pwm_led_0@0 { + reg = <0>; + ec-led-name = "EC_LED_ID_BATTERY_LED"; + }; + }; +}; + +&pwm1 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm1_gpa1_default>; + pinctrl-names = "default"; +}; + +&pwm2 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm2_gpa2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + status = "okay"; + prescaler-cx = ; + pinctrl-0 = <&pwm3_gpa3_default>; + pinctrl-names = "default"; +}; diff --git a/zephyr/program/nissa/gothrax/src/charger.c b/zephyr/program/nissa/gothrax/src/charger.c new file mode 100644 index 0000000000..c8b09bd82c --- /dev/null +++ b/zephyr/program/nissa/gothrax/src/charger.c @@ -0,0 +1,55 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "battery.h" +#include "charger.h" +#include "console.h" +#include "driver/charger/sm5803.h" +#include "extpower.h" +#include "usb_pd.h" + +#include + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +int extpower_is_present(void) +{ + int port; + int rv; + bool acok; + + for (port = 0; port < board_get_usb_pd_port_count(); port++) { + rv = sm5803_is_acok(port, &acok); + if ((rv == EC_SUCCESS) && acok) + return 1; + } + + return 0; +} + +/* + * Nereid does not have a GPIO indicating whether extpower is present, + * so detect using the charger(s). + */ +__override void board_check_extpower(void) +{ + static int last_extpower_present; + int extpower_present = extpower_is_present(); + + if (last_extpower_present ^ extpower_present) + extpower_handle_update(extpower_present); + + last_extpower_present = extpower_present; +} + +__override void board_hibernate(void) +{ + /* Shut down the chargers */ + if (board_get_usb_pd_port_count() == 2) + sm5803_hibernate(CHARGER_SECONDARY); + sm5803_hibernate(CHARGER_PRIMARY); + LOG_INF("Charger(s) hibernated"); + cflush(); +} diff --git a/zephyr/program/nissa/gothrax/src/hdmi.c b/zephyr/program/nissa/gothrax/src/hdmi.c new file mode 100644 index 0000000000..5025472c6d --- /dev/null +++ b/zephyr/program/nissa/gothrax/src/hdmi.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "nissa_hdmi.h" + +#include + +__override void nissa_configure_hdmi_power_gpios(void) +{ + /* + * Nereid versions before 2 need hdmi-en-odl to be + * pulled down to enable VCC on the HDMI port, but later + * versions (and other boards) disconnect this so + * the port's VCC directly follows en-rails-odl. Only + * configure the GPIO if needed, to save power. + */ + uint32_t board_version = 0; + + /* CBI errors ignored, will configure the pin */ + cbi_get_board_version(&board_version); + if (board_version < 2) { + nissa_configure_hdmi_vcc(); + } + + /* Still always need core rails controlled */ + nissa_configure_hdmi_rails(); +} diff --git a/zephyr/program/nissa/gothrax/src/keyboard.c b/zephyr/program/nissa/gothrax/src/keyboard.c new file mode 100644 index 0000000000..b69bb4da33 --- /dev/null +++ b/zephyr/program/nissa/gothrax/src/keyboard.c @@ -0,0 +1,29 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "ec_commands.h" + +static const struct ec_response_keybd_config nereid_kb_legacy = { + .num_top_row_keys = 10, + .action_keys = { + TK_BACK, /* T1 */ + TK_FORWARD, /* T2 */ + TK_REFRESH, /* T3 */ + TK_FULLSCREEN, /* T4 */ + TK_OVERVIEW, /* T5 */ + TK_BRIGHTNESS_DOWN, /* T6 */ + TK_BRIGHTNESS_UP, /* T7 */ + TK_VOL_MUTE, /* T8 */ + TK_VOL_DOWN, /* T9 */ + TK_VOL_UP, /* T10 */ + }, + .capabilities = KEYBD_CAP_SCRNLOCK_KEY, +}; + +__override const struct ec_response_keybd_config * +board_vivaldi_keybd_config(void) +{ + return &nereid_kb_legacy; +} diff --git a/zephyr/program/nissa/gothrax/src/usbc.c b/zephyr/program/nissa/gothrax/src/usbc.c new file mode 100644 index 0000000000..e3e18e0f33 --- /dev/null +++ b/zephyr/program/nissa/gothrax/src/usbc.c @@ -0,0 +1,329 @@ +/* Copyright 2022 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charge_state_v2.h" +#include "chipset.h" +#include "driver/charger/sm5803.h" +#include "driver/tcpm/it83xx_pd.h" +#include "driver/tcpm/ps8xxx_public.h" +#include "driver/tcpm/tcpci.h" +#include "hooks.h" +#include "system.h" +#include "usb_mux.h" + +#include + +#include + +LOG_MODULE_DECLARE(nissa, CONFIG_NISSA_LOG_LEVEL); + +/* Vconn control for integrated ITE TCPC */ +void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) +{ + /* Vconn control is only for port 0 */ + if (port) + return; + + if (cc_pin == USBPD_CC_PIN_1) + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc1_vconn), + !!enabled); + else + gpio_pin_set_dt( + GPIO_DT_FROM_NODELABEL(gpio_en_usb_c0_cc2_vconn), + !!enabled); +} + +__override bool pd_check_vbus_level(int port, enum vbus_level level) +{ + return sm5803_check_vbus_level(port, level); +} + +/* + * Putting chargers into LPM when in suspend reduces power draw by about 8mW + * per charger, but also seems critical to correct operation in source mode: + * if chargers are not in LPM when a sink is first connected, VBUS sourcing + * works even if the partner is later removed (causing LPM entry) and + * reconnected (causing LPM exit). If in LPM initially, sourcing VBUS + * consistently causes the charger to report (apparently spurious) overcurrent + * failures. + * + * In short, this is important to making things work correctly but we don't + * understand why. + */ +static void board_chargers_suspend(struct ap_power_ev_callback *const cb, + const struct ap_power_ev_data data) +{ + void (*fn)(int chgnum); + + switch (data.event) { + case AP_POWER_SUSPEND: + fn = sm5803_enable_low_power_mode; + break; + case AP_POWER_RESUME: + fn = sm5803_disable_low_power_mode; + break; + default: + LOG_WRN("%s: power event %d is not recognized", __func__, + data.event); + return; + } + + fn(CHARGER_PRIMARY); + if (board_get_charger_chip_count() > 1) + fn(CHARGER_SECONDARY); +} + +static int board_chargers_suspend_init(void) +{ + static struct ap_power_ev_callback cb = { + .handler = board_chargers_suspend, + .events = AP_POWER_SUSPEND | AP_POWER_RESUME, + }; + ap_power_ev_add_callback(&cb); + return 0; +} +SYS_INIT(board_chargers_suspend_init, APPLICATION, 0); + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && port < board_get_usb_pd_port_count()); + int i; + int old_port; + int rv; + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + old_port = charge_manager_get_active_charge_port(); + LOG_INF("Charge update: p%d -> p%d", old_port, port); + + /* Check if port is sourcing VBUS. */ + if (port != CHARGE_PORT_NONE && charger_is_sourcing_otg_power(port)) { + LOG_WRN("Skip enable p%d: already sourcing", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking on all ports except the desired one */ + for (i = 0; i < board_get_usb_pd_port_count(); i++) { + if (i == port) + continue; + + if (sm5803_vbus_sink_enable(i, 0)) + /* + * Do not early-return because this can fail during + * power-on which would put us into a loop. + */ + LOG_WRN("p%d: sink path disable failed.", i); + } + + /* Don't enable anything (stop here) if no ports were requested */ + if ((port == CHARGE_PORT_NONE) || (old_port == port)) + return EC_SUCCESS; + + /* + * Stop the charger IC from switching while changing ports. Otherwise, + * we can overcurrent the adapter we're switching to. (crbug.com/926056) + */ + if (old_port != CHARGE_PORT_NONE) + charger_discharge_on_ac(1); + + /* Enable requested charge port. */ + rv = sm5803_vbus_sink_enable(port, 1); + if (rv) + LOG_WRN("p%d: sink path enable failed: code %d", port, rv); + + /* Allow the charger IC to begin/continue switching. */ + charger_discharge_on_ac(0); + + return rv; +} + +uint16_t tcpc_get_alert_status(void) +{ + /* + * TCPC 0 is embedded in the EC and processes interrupts in the chip + * code (it83xx/intc.c). This function only needs to poll port C1 if + * present. + */ + uint16_t status = 0; + int regval; + + /* Is the C1 port present and its IRQ line asserted? */ + if (board_get_usb_pd_port_count() == 2 && + !gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + /* + * C1 IRQ is shared between BC1.2 and TCPC; poll TCPC to see if + * it asserted the IRQ. + */ + if (!tcpc_read16(1, TCPC_REG_ALERT, ®val)) { + if (regval) + status = PD_STATUS_TCPC_ALERT_1; + } + } + + return status; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + if (port < 0 || port >= board_get_usb_pd_port_count()) + return; + + prev_en = charger_is_sourcing_otg_power(port); + + /* Disable Vbus */ + charger_enable_otg_power(port, 0); + + /* Discharge Vbus if previously enabled */ + if (prev_en) + sm5803_set_vbus_disch(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + enum ec_error_list rv; + + if (port < 0 || port > board_get_usb_pd_port_count()) { + LOG_WRN("Port C%d does not exist, cannot enable VBUS", port); + return EC_ERROR_INVAL; + } + + /* Disable sinking */ + rv = sm5803_vbus_sink_enable(port, 0); + if (rv) { + LOG_WRN("C%d failed to disable sinking: %d", port, rv); + return rv; + } + + /* Disable Vbus discharge */ + rv = sm5803_set_vbus_disch(port, 0); + if (rv) { + LOG_WRN("C%d failed to clear VBUS discharge: %d", port, rv); + return rv; + } + + /* Provide Vbus */ + rv = charger_enable_otg_power(port, 1); + if (rv) { + LOG_WRN("C%d failed to enable VBUS sourcing: %d", port, rv); + return rv; + } + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp) +{ + int rv; + const int current = rp == TYPEC_RP_3A0 ? 3000 : 1500; + + rv = charger_set_otg_current_voltage(port, current, 5000); + if (rv != EC_SUCCESS) { + LOG_WRN("Failed to set source ilimit on port %d to %d: %d", + port, current, rv); + } +} + +void board_reset_pd_mcu(void) +{ + /* + * Do nothing. The integrated TCPC for C0 lacks a dedicated reset + * command, and C1 (if present) doesn't have a reset pin connected + * to the EC. + */ +} + +#define INT_RECHECK_US 5000 + +/* C0 interrupt line shared by BC 1.2 and charger */ + +static void check_c0_line(void); +DECLARE_DEFERRED(check_c0_line); + +static void notify_c0_chips(void) +{ + usb_charger_task_set_event(0, USB_CHG_EVENT_BC12); + sm5803_interrupt(0); +} + +static void check_c0_line(void) +{ + /* + * If line is still being held low, see if there's more to process from + * one of the chips + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_usb_c0_int_odl))) { + notify_c0_chips(); + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); + } +} + +void usb_c0_interrupt(enum gpio_signal s) +{ + /* Cancel any previous calls to check the interrupt line */ + hook_call_deferred(&check_c0_line_data, -1); + + /* Notify all chips using this line that an interrupt came in */ + notify_c0_chips(); + + /* Check the line again in 5ms */ + hook_call_deferred(&check_c0_line_data, INT_RECHECK_US); +} + +/* C1 interrupt line shared by BC 1.2, TCPC, and charger */ +void usb_c1_interrupt(enum gpio_signal s) +{ + /* Charger and BC1.2 are handled in board_process_pd_alert */ + schedule_deferred_pd_interrupt(1); +} + +/* + * Handle charger interrupts in the PD task. Not doing so can lead to a priority + * inversion where we fail to respond to TCPC alerts quickly enough because we + * don't get another edge on a shared IRQ until the other interrupt is cleared + * (or the IRQ is polled again), which happens in lower-priority tasks: the + * high-priority type-C handler is thus blocked on the lower-priority one(s). + * + * To avoid that, we run charger and BC1.2 interrupts synchronously alongside + * PD interrupts so they have the same priority. + */ +void board_process_pd_alert(int port) +{ + /* + * Port 0 doesn't use an external TCPC, so its interrupts don't need + * this special handling. + */ + if (port != 1) + return; + + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) { + sm5803_handle_interrupt(port); + usb_charger_task_set_event_sync(1, USB_CHG_EVENT_BC12); + } + /* + * Immediately schedule another TCPC interrupt if it seems we haven't + * cleared all pending interrupts. + */ + if (!gpio_pin_get_dt(GPIO_DT_FROM_ALIAS(gpio_usb_c1_int_odl))) + schedule_deferred_pd_interrupt(port); +} + +int pd_snk_is_vbus_provided(int port) +{ + int chg_det = 0; + + sm5803_get_chg_det(port, &chg_det); + + return chg_det; +} -- cgit v1.2.1 From 7f55c15872425d95df9d6e55fb9fab4a9a33937e Mon Sep 17 00:00:00 2001 From: Logan_Liao Date: Tue, 16 May 2023 20:04:05 +0800 Subject: uldren: Modify battery parameter This patch base on BatteryParameter_0516 to modify battery parameter. BUG=b:274750316 TEST=test battery cutoff success. Change-Id: Iab754f26bb6d6fa53b956d5e279bf64e03642ef9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4537643 Reviewed-by: Shou-Chieh Hsu Reviewed-by: Logan Liao Commit-Queue: Shou-Chieh Hsu Reviewed-by: Elthan Huang Tested-by: Logan Liao --- zephyr/dts/bindings/battery/battery-smart.yaml | 2 +- zephyr/dts/bindings/battery/byd,yt39x.yaml | 2 + zephyr/dts/bindings/battery/lgc,8ghcx.yaml | 4 +- zephyr/dts/bindings/battery/smp,atl26jgk.yaml | 2 + zephyr/dts/bindings/battery/smp,cos26jgk.yaml | 2 + .../dts/bindings/battery/sunwoda,cosmx3ctgkt.yaml | 62 ++++++++++++++++++++++ zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml | 2 + zephyr/program/nissa/uldren/overlay.dtsi | 4 +- 8 files changed, 76 insertions(+), 4 deletions(-) create mode 100644 zephyr/dts/bindings/battery/sunwoda,cosmx3ctgkt.yaml diff --git a/zephyr/dts/bindings/battery/battery-smart.yaml b/zephyr/dts/bindings/battery/battery-smart.yaml index 9c48620186..751fde1377 100644 --- a/zephyr/dts/bindings/battery/battery-smart.yaml +++ b/zephyr/dts/bindings/battery/battery-smart.yaml @@ -80,7 +80,7 @@ properties: - "smp,si03054xl" - "sunwoda,atlvkyjx" - "sunwoda,cosvkyjx" - - "sunwoda,cos3ctgkt" + - "sunwoda,cosmx3ctgkt" - "sunwoda,l22d3pg0" - "sunwoda,l22d3pg1" - "sunwoda,ctgkt" diff --git a/zephyr/dts/bindings/battery/byd,yt39x.yaml b/zephyr/dts/bindings/battery/byd,yt39x.yaml index 9f4bb4a98a..e9e38e62ee 100644 --- a/zephyr/dts/bindings/battery/byd,yt39x.yaml +++ b/zephyr/dts/bindings/battery/byd,yt39x.yaml @@ -17,6 +17,8 @@ properties: default: "BYD" device_name: default: "DELL YT39X" + ship_mode_wb_support: + default: 1 ship_mode_reg_addr: default: 0x44 ship_mode_reg_data: diff --git a/zephyr/dts/bindings/battery/lgc,8ghcx.yaml b/zephyr/dts/bindings/battery/lgc,8ghcx.yaml index 4f91a01fab..d564b00637 100644 --- a/zephyr/dts/bindings/battery/lgc,8ghcx.yaml +++ b/zephyr/dts/bindings/battery/lgc,8ghcx.yaml @@ -13,9 +13,11 @@ properties: default: "lgc,8ghcx" manuf_name: - default: "LGC-LGC3.685" + default: "LGC-LGC3.65" device_name: default: "DELL 8GHCX" + ship_mode_wb_support: + default: 1 ship_mode_reg_addr: default: 0x44 ship_mode_reg_data: diff --git a/zephyr/dts/bindings/battery/smp,atl26jgk.yaml b/zephyr/dts/bindings/battery/smp,atl26jgk.yaml index f93e132943..9f7f299a6b 100644 --- a/zephyr/dts/bindings/battery/smp,atl26jgk.yaml +++ b/zephyr/dts/bindings/battery/smp,atl26jgk.yaml @@ -17,6 +17,8 @@ properties: default: "SMP-ATL-3.61" device_name: default: "DELL 26JGK" + ship_mode_wb_support: + default: 1 ship_mode_reg_addr: default: 0x44 ship_mode_reg_data: diff --git a/zephyr/dts/bindings/battery/smp,cos26jgk.yaml b/zephyr/dts/bindings/battery/smp,cos26jgk.yaml index 67c4f5bb9c..4e0697c74e 100644 --- a/zephyr/dts/bindings/battery/smp,cos26jgk.yaml +++ b/zephyr/dts/bindings/battery/smp,cos26jgk.yaml @@ -17,6 +17,8 @@ properties: default: "SMP-COS3.63" device_name: default: "DELL 26JGK" + ship_mode_wb_support: + default: 1 ship_mode_reg_addr: default: 0x44 ship_mode_reg_data: diff --git a/zephyr/dts/bindings/battery/sunwoda,cosmx3ctgkt.yaml b/zephyr/dts/bindings/battery/sunwoda,cosmx3ctgkt.yaml new file mode 100644 index 0000000000..035ee494fc --- /dev/null +++ b/zephyr/dts/bindings/battery/sunwoda,cosmx3ctgkt.yaml @@ -0,0 +1,62 @@ +# Copyright 2023 The ChromiumOS Authors +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. + +description: "SWD-COSMX3.618 DELL CTGKT" + +compatible: "sunwoda,cosmx3ctgkt" + +include: battery-smart.yaml + +properties: + enum-name: + type: string + default: "sunwoda,cosmx3ctgkt" + + # Fuel Gauge + manuf_name: + default: "SWD-COSMX3.618" + device_name: + default: "DELL CTGKT" + ship_mode_wb_support: + default: 1 + ship_mode_reg_addr: + default: 0x44 + ship_mode_reg_data: + default: [0x0010, 0x0010] + fet_mfgacc_support: + default: 1 + fet_mfgacc_smb_block: + default: 1 + fet_reg_addr: + default: 0x0054 + fet_reg_mask: + default: 0x0006 + fet_disconnect_val: + default: 0x0000 + fet_cfet_mask: + default: 0x0004 + fet_cfet_off_val: + default: 0x0000 + + # Battery info + voltage_max: + default: 13200 + voltage_normal: + default: 11400 + voltage_min: + default: 9000 + precharge_current: + default: 256 + start_charging_min_c: + default: 0 + start_charging_max_c: + default: 50 + charging_min_c: + default: -3 + charging_max_c: + default: 60 + discharging_min_c: + default: -5 + discharging_max_c: + default: 70 diff --git a/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml b/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml index 37fc35f2dd..baf81cd446 100644 --- a/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml +++ b/zephyr/dts/bindings/battery/sunwoda,ctgkt.yaml @@ -17,6 +17,8 @@ properties: default: "SWD-ATL3.618" device_name: default: "DELL CTGKT" + ship_mode_wb_support: + default: 1 ship_mode_reg_addr: default: 0x44 ship_mode_reg_data: diff --git a/zephyr/program/nissa/uldren/overlay.dtsi b/zephyr/program/nissa/uldren/overlay.dtsi index 7e6e823b37..edff6df276 100644 --- a/zephyr/program/nissa/uldren/overlay.dtsi +++ b/zephyr/program/nissa/uldren/overlay.dtsi @@ -33,8 +33,8 @@ sunwoda_ctgkt { compatible = "sunwoda,ctgkt", "battery-smart"; }; - sunwoda_cos3ctgkt { - compatible = "sunwoda,cos3ctgkt", "battery-smart"; + sunwoda_cosmx3ctgkt { + compatible = "sunwoda,cosmx3ctgkt", "battery-smart"; }; smp_atl26jgk { compatible = "smp,atl26jgk", "battery-smart"; -- cgit v1.2.1