From d8e0677d61d059e6c80db0e526de495b7d94a22b Mon Sep 17 00:00:00 2001 From: caveh jalali Date: Tue, 21 Sep 2021 07:00:37 +0000 Subject: Revert "npcx: correct the image copies indication bits for npcx9" This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244. Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO. Original change's description: > npcx: correct the image copies indication bits for npcx9 > > In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07 > of the MDC register) to indicate what the current image copy is. > In npcx9, these two bits are used by the booter. We need to change them > to another two empty scratch bits which are not used by the booter. > > BUG=b:165777478 > BRANCH=none > TEST=pass "make buildall" > TEST=check the related bits changed by "sysump ro" and "sysjump rw" > > Signed-off-by: Jun Lin > Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119 > Tested-by: CH Lin > Reviewed-by: caveh jalali > Auto-Submit: CH Lin > Commit-Queue: caveh jalali Bug: b:165777478 Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266 Bot-Commit: Rubber Stamper Tested-by: caveh jalali Commit-Queue: caveh jalali --- chip/npcx/registers-npcx5.h | 8 -------- chip/npcx/registers-npcx7.h | 8 -------- chip/npcx/registers-npcx9.h | 8 -------- chip/npcx/registers.h | 8 ++++++++ zephyr/shim/chip/npcx/system_external_storage.c | 8 -------- 5 files changed, 8 insertions(+), 32 deletions(-) diff --git a/chip/npcx/registers-npcx5.h b/chip/npcx/registers-npcx5.h index c441c1c926..3d241a1984 100644 --- a/chip/npcx/registers-npcx5.h +++ b/chip/npcx/registers-npcx5.h @@ -87,14 +87,6 @@ #define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ - -/* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) - -/* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - #define NPCX_ITIM32_BASE_ADDR 0x400BC000 #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers-npcx7.h b/chip/npcx/registers-npcx7.h index 535abfbf0f..cbd9be30dc 100644 --- a/chip/npcx/registers-npcx7.h +++ b/chip/npcx/registers-npcx7.h @@ -104,14 +104,6 @@ #define NPCX_IRQ_WKINTD_2 NPCX_IRQ_63 /* Modules Map */ - -/* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) - -/* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 0 -#define NPCX_FWCTRL_FW_SLOT 1 - #define NPCX_ITIM32_BASE_ADDR 0x400BC000 #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400C4000 + ((mdl) * 0x2000L)) #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers-npcx9.h b/chip/npcx/registers-npcx9.h index a013a8b645..296f1af25c 100644 --- a/chip/npcx/registers-npcx9.h +++ b/chip/npcx/registers-npcx9.h @@ -90,14 +90,6 @@ #define LCT_WUI_MASK MASK_PIN7 /* Modules Map */ - -/* Miscellaneous Device Control (MDC) registers */ -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x005) - -/* MDC register fields */ -#define NPCX_FWCTRL_RO_REGION 1 -#define NPCX_FWCTRL_FW_SLOT 2 - #define NPCX_CR_UART_BASE_ADDR(mdl) (0x400E0000 + ((mdl) * 0x2000L)) #define NPCX_LCT_BASE_ADDR 0x400D7000 #define NPCX_SMB_BASE_ADDR(mdl) (((mdl) < 2) ? \ diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index f0c241e7f9..374e9d58ba 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -174,6 +174,14 @@ #define NPCX_IRQ_COUNT 64 +/******************************************************************************/ +/* Miscellaneous Device Control (MDC) registers */ +#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) + +/* MDC register fields */ +#define NPCX_FWCTRL_RO_REGION 0 +#define NPCX_FWCTRL_FW_SLOT 1 + /******************************************************************************/ /* High Frequency Clock Generator (HFCG) registers */ #define NPCX_HFCGCTRL REG8(NPCX_HFCG_BASE_ADDR + 0x000) diff --git a/zephyr/shim/chip/npcx/system_external_storage.c b/zephyr/shim/chip/npcx/system_external_storage.c index bce82b8841..b53db04e18 100644 --- a/zephyr/shim/chip/npcx/system_external_storage.c +++ b/zephyr/shim/chip/npcx/system_external_storage.c @@ -12,17 +12,9 @@ /* TODO (b:179900857) Make this implementation not npcx specific. */ #define NPCX_MDC_BASE_ADDR 0x4000C000 -#ifdef CONFIG_SOC_SERIES_NPCX7 #define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x007) #define NPCX_FWCTRL_RO_REGION 0 #define NPCX_FWCTRL_FW_SLOT 1 -#elif defined(CONFIG_SOC_SERIES_NPCX9) -#define NPCX_FWCTRL REG8(NPCX_MDC_BASE_ADDR + 0x005) -#define NPCX_FWCTRL_RO_REGION 1 -#define NPCX_FWCTRL_FW_SLOT 2 -#else -#error "Unsupported NPCX SoC series." -#endif void system_jump_to_booter(void) { -- cgit v1.2.1