From ddeaab3fb8d32d5028970578345772dc2300ab34 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Tue, 23 Apr 2019 09:32:15 -0600 Subject: ish: refactor IPC usage of REG macros into registers.h This is the final CL needed to resolve b:130573158. BUG=b:130573158 BRANCH=none TEST=arcada_ish functions as normal after changes Change-Id: Ia4cc9bfa95938b9f57fc1cd241cd6821b42a3ce6 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/1578435 Reviewed-by: Jett Rink Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1598522 Commit-Queue: Jett Rink Tested-by: Jett Rink --- chip/ish/aontaskfw/ish_aontask.c | 6 ++-- chip/ish/ipc_heci.c | 66 +++++++++++++++------------------------- chip/ish/ish_fwst.h | 36 +++++++++++----------- chip/ish/registers.h | 30 +++++++++--------- 4 files changed, 60 insertions(+), 78 deletions(-) diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c index 4bfd6fcab4..f90ec94d8c 100644 --- a/chip/ish/aontaskfw/ish_aontask.c +++ b/chip/ish/aontaskfw/ish_aontask.c @@ -541,7 +541,7 @@ static void handle_d3(void) static void handle_reset(int pm_state) { /* disable CSME CSR irq */ - REG32(IPC_PIMR) &= ~IPC_PIMR_CSME_CSR_BIT; + IPC_PIMR &= ~IPC_PIMR_CSME_CSR_BIT; /* power off main SRAM */ sram_power(0); @@ -549,10 +549,10 @@ static void handle_reset(int pm_state) while (1) { /* check if host ish driver already set the DMA enable flag */ - if (REG32(IPC_ISH_RMP2) & DMA_ENABLED_MASK) { + if (IPC_ISH_RMP2 & DMA_ENABLED_MASK) { /* clear ISH2HOST doorbell register */ - REG32(IPC_ISH2HOST_DOORBELL) = 0; + *IPC_ISH2HOST_DOORBELL_ADDR = 0; /* clear error register in MISC space */ MISC_ISH_ECC_ERR_SRESP = 1; diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index aaf30af61d..0086488155 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -135,10 +135,10 @@ struct ipc_msg_event { * This is per-IPC context. */ struct ipc_if_ctx { - uint32_t in_msg_reg; - uint32_t out_msg_reg; - uint32_t in_drbl_reg; - uint32_t out_drbl_reg; + volatile uint8_t *in_msg_reg; + volatile uint8_t *out_msg_reg; + volatile uint32_t *in_drbl_reg; + volatile uint32_t *out_drbl_reg; uint32_t clr_busy_bit; uint32_t pimr_2ish_bit; uint32_t pimr_2host_clearing_bit; @@ -157,10 +157,10 @@ struct ipc_if_ctx { /* list of peer contexts */ static struct ipc_if_ctx ipc_peer_ctxs[IPC_PEERS_COUNT] = { [IPC_PEER_ID_HOST] = { - .in_msg_reg = IPC_HOST2ISH_MSG_REGS, - .out_msg_reg = IPC_ISH2HOST_MSG_REGS, - .in_drbl_reg = IPC_HOST2ISH_DOORBELL, - .out_drbl_reg = IPC_ISH2HOST_DOORBELL, + .in_msg_reg = IPC_HOST2ISH_MSG_BASE, + .out_msg_reg = IPC_ISH2HOST_MSG_BASE, + .in_drbl_reg = IPC_HOST2ISH_DOORBELL_ADDR, + .out_drbl_reg = IPC_ISH2HOST_DOORBELL_ADDR, .clr_busy_bit = IPC_DB_CLR_STS_ISH2HOST_BIT, .pimr_2ish_bit = IPC_PIMR_HOST2ISH_BIT, .pimr_2host_clearing_bit = IPC_PIMR_ISH2HOST_CLR_BIT, @@ -183,24 +183,24 @@ static inline struct ipc_if_ctx *ipc_handle_to_if_ctx(const ipc_handle_t handle) static inline void ipc_enable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) { - REG32(IPC_PIMR) |= ctx->pimr_2ish_bit; + IPC_PIMR |= ctx->pimr_2ish_bit; } static inline void ipc_disable_pimr_db_interrupt(const struct ipc_if_ctx *ctx) { - REG32(IPC_PIMR) &= ~ctx->pimr_2ish_bit; + IPC_PIMR &= ~ctx->pimr_2ish_bit; } static inline void ipc_enable_pimr_clearing_interrupt( const struct ipc_if_ctx *ctx) { - REG32(IPC_PIMR) |= ctx->pimr_2host_clearing_bit; + IPC_PIMR |= ctx->pimr_2host_clearing_bit; } static inline void ipc_disable_pimr_clearing_interrupt( const struct ipc_if_ctx *ctx) { - REG32(IPC_PIMR) &= ~ctx->pimr_2host_clearing_bit; + IPC_PIMR &= ~ctx->pimr_2host_clearing_bit; } static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx, @@ -208,25 +208,8 @@ static void write_payload_and_ring_drbl(const struct ipc_if_ctx *ctx, const uint8_t *payload, size_t payload_size) { - uint32_t msg_idx = 0; - - /* write in 32-bits unit */ - while (payload_size >= sizeof(uint32_t)) { - REG32(ctx->out_msg_reg + msg_idx) = - *(uint32_t *)(payload + msg_idx); - msg_idx += sizeof(uint32_t); - payload_size -= sizeof(uint32_t); - } - - /* write leftovers in 8-bits unit */ - while (payload_size) { - REG8(ctx->out_msg_reg + msg_idx) = - *(uint8_t *)(payload + msg_idx); - msg_idx++; - payload_size--; - } - - REG32(ctx->out_drbl_reg) = drbl; + memcpy((void *)(ctx->out_msg_reg), payload, payload_size); + *(ctx->out_drbl_reg) = drbl; } static int ipc_write_raw_timestamp(struct ipc_if_ctx *ctx, uint32_t drbl, @@ -314,7 +297,7 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, struct ipc_msg *msg; uint32_t drbl_val; - drbl_val = REG32(ctx->in_drbl_reg); + drbl_val = *(ctx->in_drbl_reg); payload_size = IPC_DB_MSG_LENGTH(drbl_val); if (payload_size > IPC_MAX_PAYLOAD_SIZE) { @@ -352,7 +335,6 @@ static int ipc_get_protocol_data(const struct ipc_if_ctx *ctx, break; case IPC_PROTOCOL_MNG: src = (uint8_t *)ctx->in_msg_reg; - msg = (struct ipc_msg *)buf; msg->drbl = drbl_val; dest = msg->payload; @@ -381,7 +363,7 @@ static void handle_msg_recv_interrupt(const uint32_t peer_id) ctx = ipc_get_if_ctx(peer_id); ipc_disable_pimr_db_interrupt(ctx); - drbl_val = REG32(ctx->in_drbl_reg); + drbl_val = *(ctx->in_drbl_reg); protocol = IPC_DB_PROTOCOL(drbl_val); payload_size = IPC_DB_MSG_LENGTH(drbl_val); @@ -398,7 +380,7 @@ static void handle_msg_recv_interrupt(const uint32_t peer_id) } else { CPRINTS("discard msg (%d) : %d", protocol, invalid_msg); - REG32(ctx->in_drbl_reg) = 0; + *(ctx->in_drbl_reg) = 0; set_pimr_and_send_rx_complete(ctx); } } @@ -416,7 +398,7 @@ static void handle_busy_clear_interrupt(const uint32_t peer_id) * Resetting interrupt status bit should be done * before sending an item in tx_queue. */ - REG32(IPC_BUSY_CLEAR) = ctx->clr_busy_bit; + IPC_BUSY_CLEAR = ctx->clr_busy_bit; /* * No need to use sync mechanism here since the accesing the queue @@ -461,8 +443,8 @@ static void handle_busy_clear_interrupt(const uint32_t peer_id) */ static void ipc_host2ish_isr(void) { - uint32_t pisr = REG32(IPC_PISR); - uint32_t pimr = REG32(IPC_PIMR); + uint32_t pisr = IPC_PISR; + uint32_t pimr = IPC_PIMR; #ifdef CHIP_FAMILY_ISH5 /* @@ -485,8 +467,8 @@ DECLARE_IRQ(ISH_IPC_HOST2ISH_IRQ, ipc_host2ish_isr); static void ipc_host2ish_busy_clear_isr(void) { - uint32_t busy_clear = REG32(IPC_BUSY_CLEAR); - uint32_t pimr = REG32(IPC_PIMR); + uint32_t busy_clear = IPC_BUSY_CLEAR; + uint32_t pimr = IPC_PIMR; if ((busy_clear & IPC_DB_CLR_STS_ISH2HOST_BIT) && (pimr & IPC_PIMR_ISH2HOST_CLR_BIT)) @@ -631,7 +613,7 @@ static int do_ipc_read(struct ipc_if_ctx *ctx, const uint32_t protocol, len = ipc_get_protocol_data(ctx, protocol, buf, buf_size); - REG32(ctx->in_drbl_reg) = 0; + *(ctx->in_drbl_reg) = 0; set_pimr_and_send_rx_complete(ctx); return len; @@ -684,7 +666,7 @@ int ipc_read(const ipc_handle_t handle, void *buf, const size_t buf_size, return -EC_ERROR_UNKNOWN; } else { /* check if msg for the protocol is available */ - drbl_val = REG32(ctx->in_drbl_reg); + drbl_val = *(ctx->in_drbl_reg); drbl_protocol = IPC_DB_PROTOCOL(drbl_val); if (!(protocol == drbl_protocol) || !IPC_DB_BUSY(drbl_val)) return -IPC_ERR_MSG_NOT_AVAILABLE; diff --git a/chip/ish/ish_fwst.h b/chip/ish/ish_fwst.h index c05caaefcb..edc347aa12 100644 --- a/chip/ish/ish_fwst.h +++ b/chip/ish/ish_fwst.h @@ -99,43 +99,43 @@ enum { /* get ISH FW status register */ static inline uint32_t ish_fwst_get(void) { - return REG32(IPC_ISH_FWSTS); + return IPC_ISH_FWSTS; } /* set IPC link up */ static inline void ish_fwst_set_ilup(void) { - REG32(IPC_ISH_FWSTS) |= (1<> IPC_ISH_FWSTS_FAIL_REASON_SHIFT; } /* set reset id */ static inline void ish_fwst_set_reset_id(uint32_t val) { - uint32_t fwst = REG32(IPC_ISH_FWSTS); + uint32_t fwst = IPC_ISH_FWSTS; - REG32(IPC_ISH_FWSTS) = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) | - (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); + IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_RESET_ID_MASK) | + (val << IPC_ISH_FWSTS_RESET_ID_SHIFT); } /* get reset id */ static inline uint32_t ish_fwst_get_reset_id(void) { - return (REG32(IPC_ISH_FWSTS) & IPC_ISH_FWSTS_RESET_ID_MASK) + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_RESET_ID_MASK) >> IPC_ISH_FWSTS_RESET_ID_SHIFT; } /* set general fw status */ static inline void ish_fwst_set_fw_status(uint32_t val) { - uint32_t fwst = REG32(IPC_ISH_FWSTS); + uint32_t fwst = IPC_ISH_FWSTS; - REG32(IPC_ISH_FWSTS) = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) | - (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); + IPC_ISH_FWSTS = (fwst & ~IPC_ISH_FWSTS_FW_STATUS_MASK) | + (val << IPC_ISH_FWSTS_FW_STATUS_SHIFT); } /* get general fw status */ static inline uint32_t ish_fwst_get_fw_status(void) { - return (REG32(IPC_ISH_FWSTS) & IPC_ISH_FWSTS_FW_STATUS_MASK) + return (IPC_ISH_FWSTS & IPC_ISH_FWSTS_FW_STATUS_MASK) >> IPC_ISH_FWSTS_FW_STATUS_SHIFT; } diff --git a/chip/ish/registers.h b/chip/ish/registers.h index 7e6b580d76..7881fd3fe7 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -130,25 +130,25 @@ enum ish_i2c_port { #endif /* IPC_Registers */ -#define IPC_PISR (ISH_IPC_BASE + 0x0) +#define IPC_PISR REG32(ISH_IPC_BASE + 0x0) #define IPC_PISR_HOST2ISH_BIT BIT(0) -#define IPC_PIMR (ISH_IPC_BASE + 0x4) +#define IPC_PIMR REG32(ISH_IPC_BASE + 0x4) #define IPC_PIMR_HOST2ISH_BIT BIT(0) #define IPC_PIMR_ISH2HOST_CLR_BIT BIT(11) #define IPC_PIMR_CSME_CSR_BIT BIT(23) -#define IPC_ISH2HOST_MSG_REGS (ISH_IPC_BASE + 0x60) -#define IPC_ISH_FWSTS (ISH_IPC_BASE + 0x34) -#define IPC_HOST2ISH_DOORBELL (ISH_IPC_BASE + 0x48) -#define IPC_HOST2ISH_MSG_REGS (ISH_IPC_BASE + 0xE0) -#define IPC_ISH2HOST_DOORBELL (ISH_IPC_BASE + 0x54) -#define IPC_ISH2PMC_DOORBELL (ISH_IPC_BASE + 0x58) -#define IPC_ISH2PMC_MSG_REGS (ISH_IPC_BASE + 0x260) -#define IPC_ISH_RMP0 (ISH_IPC_BASE + 0x360) -#define IPC_ISH_RMP1 (ISH_IPC_BASE + 0x364) -#define IPC_ISH_RMP2 (ISH_IPC_BASE + 0x368) +#define IPC_ISH2HOST_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0x60) +#define IPC_ISH_FWSTS REG32(ISH_IPC_BASE + 0x34) +#define IPC_HOST2ISH_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x48) +#define IPC_HOST2ISH_MSG_BASE REG8_ADDR(ISH_IPC_BASE + 0xE0) +#define IPC_ISH2HOST_DOORBELL_ADDR REG32_ADDR(ISH_IPC_BASE + 0x54) +#define IPC_ISH2PMC_DOORBELL REG32(ISH_IPC_BASE + 0x58) +#define IPC_ISH2PMC_MSG_BASE (ISH_IPC_BASE + 0x260) +#define IPC_ISH_RMP0 REG32(ISH_IPC_BASE + 0x360) +#define IPC_ISH_RMP1 REG32(ISH_IPC_BASE + 0x364) +#define IPC_ISH_RMP2 REG32(ISH_IPC_BASE + 0x368) #define DMA_ENABLED_MASK BIT(0) -#define IPC_BUSY_CLEAR (ISH_IPC_BASE + 0x378) +#define IPC_BUSY_CLEAR REG32(ISH_IPC_BASE + 0x378) #define IPC_DB_CLR_STS_ISH2HOST_BIT BIT(0) #define IPC_UMA_RANGE_LOWER_0 REG32(ISH_IPC_BASE + 0x380) @@ -340,10 +340,10 @@ enum ish_i2c_port { #if defined(CHIP_FAMILY_ISH3) /* on ISH3, reused ISH2PMC IPC message registers */ -#define SNOWBALL_BASE IPC_ISH2PMC_MSG_REGS +#define SNOWBALL_BASE IPC_ISH2PMC_MSG_BASE #else /* from ISH4, used reserved rom part of AON memory */ -#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START +#define SNOWBALL_BASE CONFIG_ISH_AON_SRAM_ROM_START #endif /** -- cgit v1.2.1