From eb1327ea0ccf839cb1391ef86b7c4a5b7c0491c6 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 18 Aug 2015 14:43:17 -0500 Subject: glados: don't pull up SLP_S0_L The SLP_S0_L signal lives in the primary power well of skylake while the EC's VCC is on the DSW rail. If SLP_S0_L is pulled up then there is leakage into the primary well when it's not on. BUG=chrome-os-partner:44098 BRANCH=None TEST=Built and booted glados. Default powerindebug state shows SLP_S0_L low when in deep sleep states. Change-Id: If9c7972fb6a8b8f90738c1c0f7eea6cf2373d64b Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/293842 Reviewed-by: Duncan Laurie --- board/glados/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/glados/gpio.inc b/board/glados/gpio.inc index 66873b68c7..66fa79072a 100644 --- a/board/glados/gpio.inc +++ b/board/glados/gpio.inc @@ -14,7 +14,7 @@ GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt) GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) +GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt) GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VOLUME_UP_L, PIN(31), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) GPIO_INT(VOLUME_DOWN_L, PIN(47), GPIO_INT_FALLING | GPIO_PULL_UP, button_interrupt) -- cgit v1.2.1