From ec339489d1f0d67f43934949a9b7fb271a043546 Mon Sep 17 00:00:00 2001 From: Harry Cutts Date: Tue, 22 Jun 2021 17:37:52 -0700 Subject: =?UTF-8?q?stm32:=20rename=20CONFIG=5FSTM32=5FSPI1=5FMASTER=20to?= =?UTF-8?q?=20=E2=80=A6CONTROLLER?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In line with OSHWA terminology. BUG=b:181607131 TEST=make -j BOARD=hammer BRANCH=none Change-Id: I6d212e60d5aceb8497f00520b693006cc1af2d45 Signed-off-by: Harry Cutts Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981123 Reviewed-by: caveh jalali --- board/hammer/board.h | 4 ++-- chip/stm32/spi_master-stm32h7.c | 10 +++++----- chip/stm32/spi_master.c | 8 ++++---- include/config.h | 6 +++--- util/config_allowed.txt | 2 +- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/board/hammer/board.h b/board/hammer/board.h index 4a16983b54..3282425d9e 100644 --- a/board/hammer/board.h +++ b/board/hammer/board.h @@ -238,10 +238,10 @@ #define CONFIG_USB_SPI #define CONFIG_SPI_CONTROLLER #define CONFIG_SPI_HALFDUPLEX -#define CONFIG_STM32_SPI1_MASTER +#define CONFIG_STM32_SPI1_CONTROLLER #define CONFIG_SPI_TOUCHPAD_PORT 0 #define SPI_ST_TP_DEVICE_ID 0 -/* Enable SPI master xfer command */ +/* Enable SPI controller xfer command */ #define CONFIG_CMD_SPI_XFER #define CONFIG_TOUCHPAD #define CONFIG_TOUCHPAD_ST diff --git a/chip/stm32/spi_master-stm32h7.c b/chip/stm32/spi_master-stm32h7.c index a031ff76c6..4195dc595a 100644 --- a/chip/stm32/spi_master-stm32h7.c +++ b/chip/stm32/spi_master-stm32h7.c @@ -18,7 +18,7 @@ /* SPI ports are used as master */ static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER STM32_SPI1_REGS, #endif STM32_SPI2_REGS, @@ -28,7 +28,7 @@ static stm32_spi_regs_t *SPI_REGS[] = { /* DMA request mapping on channels */ static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER DMAMUX1_REQ_SPI1_TX, #endif DMAMUX1_REQ_SPI2_TX, @@ -36,7 +36,7 @@ static uint8_t dma_req_tx[ARRAY_SIZE(SPI_REGS)] = { DMAMUX1_REQ_SPI4_TX, }; static uint8_t dma_req_rx[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER DMAMUX1_REQ_SPI1_RX, #endif DMAMUX1_REQ_SPI2_RX, @@ -49,7 +49,7 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; #define SPI_TRANSACTION_TIMEOUT_USEC (800 * MSEC) static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->txdr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT @@ -70,7 +70,7 @@ static const struct dma_option dma_tx_option[] = { }; static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->rxdr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c index 86185680cf..8943c0c682 100644 --- a/chip/stm32/spi_master.c +++ b/chip/stm32/spi_master.c @@ -27,7 +27,7 @@ /* The second (and third if available) SPI port are used as master */ static stm32_spi_regs_t *SPI_REGS[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER STM32_SPI1_REGS, #endif STM32_SPI2_REGS, @@ -39,7 +39,7 @@ static stm32_spi_regs_t *SPI_REGS[] = { #ifdef CHIP_FAMILY_STM32L4 /* DMA request mapping on channels */ static uint8_t dma_req[ARRAY_SIZE(SPI_REGS)] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER /* SPI1 */ 1, #endif /* SPI2 */ 1, @@ -59,7 +59,7 @@ static struct mutex spi_mutex[ARRAY_SIZE(SPI_REGS)]; #endif static const struct dma_option dma_tx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER { STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT @@ -81,7 +81,7 @@ static const struct dma_option dma_tx_option[] = { }; static const struct dma_option dma_rx_option[] = { -#ifdef CONFIG_STM32_SPI1_MASTER +#ifdef CONFIG_STM32_SPI1_CONTROLLER { STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT diff --git a/include/config.h b/include/config.h index 661e1de680..58bf1340f1 100644 --- a/include/config.h +++ b/include/config.h @@ -3639,11 +3639,11 @@ /* SPI controller feature */ #undef CONFIG_SPI_CONTROLLER -/* SPI master halfduplex/3-wire mode */ +/* SPI controller halfduplex/3-wire mode */ #undef CONFIG_SPI_HALFDUPLEX -/* Support STM32 SPI1 as master. */ -#undef CONFIG_STM32_SPI1_MASTER +/* Support STM32 SPI1 as controller. */ +#undef CONFIG_STM32_SPI1_CONTROLLER /* Support MCHP MEC family GP-SPI master(s) * Define to 0x01 for GPSPI0 only. diff --git a/util/config_allowed.txt b/util/config_allowed.txt index df3f01be04..903cd339ac 100644 --- a/util/config_allowed.txt +++ b/util/config_allowed.txt @@ -877,7 +877,7 @@ CONFIG_STM32L_FAKE_HIBERNATE CONFIG_STM32_CHARGER_DETECT CONFIG_STM32_CLOCK_HSE_HZ CONFIG_STM32_CLOCK_LSE -CONFIG_STM32_SPI1_MASTER +CONFIG_STM32_SPI1_CONTROLLER CONFIG_STM_HWTIMER32 CONFIG_STREAM_SIGNATURE CONFIG_STREAM_USART -- cgit v1.2.1