From ed5290019ce657b8b937b4f2d1f128234105b5e3 Mon Sep 17 00:00:00 2001 From: Aseda Aboagye Date: Wed, 7 Jun 2017 13:11:58 -0700 Subject: board: Add initial support for zoombini. This commit adds the initial board support for zoombini. BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I38a108d607ed1a33a0e5b588d4d463026919ac20 Signed-off-by: Aseda Aboagye Reviewed-on: https://chromium-review.googlesource.com/564800 Commit-Ready: Aseda Aboagye Tested-by: Aseda Aboagye Reviewed-by: Shawn N --- board/zoombini/battery.c | 27 +++ board/zoombini/board.c | 240 ++++++++++++++++++++++++ board/zoombini/board.h | 141 ++++++++++++++ board/zoombini/build.mk | 13 ++ board/zoombini/ec.tasklist | 35 ++++ board/zoombini/gpio.inc | 93 ++++++++++ board/zoombini/usb_pd_policy.c | 413 +++++++++++++++++++++++++++++++++++++++++ include/config.h | 15 +- 8 files changed, 966 insertions(+), 11 deletions(-) create mode 100644 board/zoombini/battery.c create mode 100644 board/zoombini/board.c create mode 100644 board/zoombini/board.h create mode 100644 board/zoombini/build.mk create mode 100644 board/zoombini/ec.tasklist create mode 100644 board/zoombini/gpio.inc create mode 100644 board/zoombini/usb_pd_policy.c diff --git a/board/zoombini/battery.c b/board/zoombini/battery.c new file mode 100644 index 0000000000..e12b9730bb --- /dev/null +++ b/board/zoombini/battery.c @@ -0,0 +1,27 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery.h" + +/* Battery info for proto */ +static const struct battery_info info = { + .voltage_max = 13200, + .voltage_normal = 11250, + .voltage_min = 9000, + .precharge_current = 189, + .start_charging_min_c = 0, + .start_charging_max_c = 60, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = -20, + .discharging_max_c = 60, +}; + +const struct battery_info *battery_get_info(void) +{ + return &info; +} diff --git a/board/zoombini/board.c b/board/zoombini/board.c new file mode 100644 index 0000000000..5ee427a69a --- /dev/null +++ b/board/zoombini/board.c @@ -0,0 +1,240 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zoombini board-specific configuration */ + +#include "adc_chip.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "charge_state_v2.h" +#include "common.h" +#include "console.h" +#include "compile_time_macros.h" +#include "driver/tcpm/ps8xxx.h" +#include "ec_commands.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "power.h" +#include "power_button.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "registers.h" +#include "switch.h" +#include "tcpci.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +static void tcpc_alert_event(enum gpio_signal s) +{ +#ifdef HAS_TASK_PDCMD + /* Exchange status with TCPCs */ + host_command_pd_send_status(PD_CHARGE_NO_CHANGE); +#endif +} + +#include "gpio_list.h" + +/* TODO(aaboagye): Handle PSL? */ +const enum gpio_signal hibernate_wake_pins[] = { + GPIO_LID_OPEN, + GPIO_AC_PRESENT, + GPIO_POWER_BUTTON_L, +}; +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + +const struct adc_t adc_channels[] = { + [ADC_TEMP_SENSOR_SOC] = { + "SOC", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, + + [ADC_TEMP_SENSOR_CHARGER] = { + "CHARGER", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, +}; + +/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ +const struct pwm_t pwm_channels[] = { + [PWM_CH_LED_GREEN] = { 0, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_LED_RED] = { 2, PWM_CONFIG_DSLEEP, 100 }, + [PWM_CH_KB_BL] = { 3, 0, 100}, +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +/* Power signal list. Must match order of enum power_signal. */ +const struct power_signal_info power_signal_list[] = { + /* TODO(aaboagye): consider eSPI VW signals. */ + {GPIO_PCH_SLP_S3_L, 1, "SLP_S3_DEASSERTED"}, + {GPIO_PCH_SLP_S4_L, 1, "SLP_S4_DEASSERTED"}, + {GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS_DEASSERTED"}, + {GPIO_RSMRST_L_PGOOD, 1, "RSMRST_L_PGOOD"}, + {GPIO_PMIC_DPWROK, 1, "PMIC_DPWROK"}, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +/* I2C port map. */ +const struct i2c_port_t i2c_ports[] = { + {"power", I2C_PORT_POWER, 400, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, + {"pmic", I2C_PORT_PMIC, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, + {"tcpc0", I2C_PORT_TCPC0, 1000, GPIO_I2C5_SCL, GPIO_I2C5_SDA}, + {"tcpc1", I2C_PORT_TCPC1, 1000, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, + {"tcpc2", I2C_PORT_TCPC2, 1000, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + /* Extra delay when KSO2 is tied to Cr50. */ + .output_settle_us = 60, /* TODO(aaboagye): verify this is sufficient. */ + .debounce_down_us = 6 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 1500, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = SECOND, + .actual_key_mask = { + 0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xc8 /* full set with lock key */ + }, +}; + +const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { + { + .i2c_host_port = I2C_PORT_TCPC0, + .i2c_slave_addr = 0x16, + .drv = &tcpci_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, + + { + .i2c_host_port = I2C_PORT_TCPC1, + .i2c_slave_addr = 0x16, + .drv = &tcpci_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, + + { + .i2c_host_port = I2C_PORT_TCPC2, + .i2c_slave_addr = 0x16, + .drv = &tcpci_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, +}; + +/* The port_addr members are PD port numbers, not I2C port numbers. */ +struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { + { + .port_addr = 0, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, + + { + .port_addr = 1, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, + + { + .port_addr = 2, + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + }, +}; + +static void board_chipset_startup(void) +{ + /* Enable trackpad. */ + gpio_set_level(GPIO_EN_PP3300_TRACKPAD, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_chipset_startup, HOOK_PRIO_DEFAULT); + +static void board_chipset_shutdown(void) +{ + /* Disable trackpad. */ + gpio_set_level(GPIO_EN_PP3300_TRACKPAD, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); + +void board_reset_pd_mcu(void) +{ + /* GPIO_USB_PD_RST_L resets all the TCPCs. */ + gpio_set_level(GPIO_USB_PD_RST_L, 0); + msleep(10); /* TODO(aaboagye): Verify min hold time. */ + gpio_set_level(GPIO_USB_PD_RST_L, 1); +} + +int board_set_active_charge_port(int port) +{ + int is_real_port = (port >= 0 && + port < CONFIG_USB_PD_PORT_COUNT); + + if (!is_real_port && port != CHARGE_PORT_NONE) + return EC_ERROR_INVAL; + + CPRINTS("New chg p%d", port); + + if (port == CHARGE_PORT_NONE) { + /* Disable all ports. */ + gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1); + gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1); + gpio_set_level(GPIO_USB_C2_CHARGE_EN_L, 1); + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (((port == 0) && gpio_get_level(GPIO_USB_C0_5V_EN)) || + ((port == 1) && gpio_get_level(GPIO_USB_C1_5V_EN)) || + ((port == 2) && gpio_get_level(GPIO_USB_C2_5V_EN))) { + CPRINTF("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* Disable other charge ports and enable requested port. */ + gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, port != 0); + gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, port != 1); + gpio_set_level(GPIO_USB_C2_CHARGE_EN_L, port != 2); + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + /* + * Ignore lower charge ceiling on PD transition if our battery is + * critical, as we may brownout. + */ + if (supplier == CHARGE_SUPPLIER_PD && + charge_ma < 1500 && + charge_get_percent() < CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON) { + CPRINTS("Using max ilim %d", max_ma); + charge_ma = max_ma; + } + + charge_set_input_current_limit(MAX(charge_ma, + CONFIG_CHARGER_INPUT_CURRENT), + charge_mv); +} + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_get_level(GPIO_USB_C0_PD_INT_L)) + status |= PD_STATUS_TCPC_ALERT_0; + if (!gpio_get_level(GPIO_USB_C1_PD_INT_L)) + status |= PD_STATUS_TCPC_ALERT_1; + if (!gpio_get_level(GPIO_USB_C2_PD_INT_L)) + status |= PD_STATUS_TCPC_ALERT_2; + + return status; +} diff --git a/board/zoombini/board.h b/board/zoombini/board.h new file mode 100644 index 0000000000..0dfd73373f --- /dev/null +++ b/board/zoombini/board.h @@ -0,0 +1,141 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zoombini board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Optional features */ +#define CONFIG_BRINGUP +#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands. */ + +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +#define CONFIG_FLASH_SIZE (512 * 1024) /* It's really 1MB. */ +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* EC Modules */ +#define CONFIG_ADC +#define CONFIG_ESPI +#define CONFIG_I2C +#define CONFIG_LPC +#define CONFIG_PWM + +#define CONFIG_BATTERY_SMART +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L + +#define CONFIG_CHARGER +#define CONFIG_CHARGER_V2 +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 1 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +/* TODO(aaboagye): add when BC 1.2 stuff ready. */ +#if 0 +#define CONFIG_USB_CHARGER +#endif /* 0 */ + +#define CONFIG_CHIPSET_CANNONLAKE +#define CONFIG_CHIPSET_RESET_HOOK +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 +#define CONFIG_UART_HOST 0 + +#define CONFIG_I2C_MASTER + +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_8042 +#define CONFIG_SWITCH + +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_PORT_COUNT 3 +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_LOG_SIZE 512 +/* TODO(aaboagye): What about CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT? */ +#define CONFIG_USB_PD_VBUS_DETECT_TCPC +#define CONFIG_USB_PD_TCPM_PS8805 +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* Define typical operating power and max power. */ +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_POWER_MW 45000 +#define PD_OPERATING_POWER_MW 15000 +#define PD_VCONN_SWAP_DELAY 5000 /* us */ + +/* TODO(aaboagye): Verify these timings... */ +/* + * delay to turn on the power supply max is ~16ms. + * delay to turn off the power supply max is about ~180ms. + */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ + +#define CONFIG_WIRELESS +#define WIRELESS_GPIO_WLAN_POWER GPIO_EN_PP3300_WLAN +#define WIRELESS_GPIO_WWAN_POWER GPIO_EN_PP3300_WWAN + +/* I2C Ports */ +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_PMIC NPCX_I2C_PORT3_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT5_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC2 NPCX_I2C_PORT2_0 + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "registers.h" + +/* ADC signal */ +enum adc_channel { + ADC_VBUS = 0, + ADC_TEMP_SENSOR_SOC, + ADC_TEMP_SENSOR_CHARGER, + ADC_CH_COUNT +}; + +enum pwm_channel { + PWM_CH_LED_GREEN = 0, + PWM_CH_LED_RED, + PWM_CH_KB_BL, + PWM_CH_COUNT +}; + +enum power_signal { + X86_SLP_S3_DEASSERTED, + X86_SLP_S4_DEASSERTED, + X86_SLP_SUS_DEASSERTED, + X86_RSMRST_L_PGOOD, + X86_PMIC_DPWROK, + POWER_SIGNAL_COUNT +}; + +/* Reset all TCPCs. */ +void board_reset_pd_mcu(void); + +#endif /* !defined(__ASSEMBLER__) */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/zoombini/build.mk b/board/zoombini/build.mk new file mode 100644 index 0000000000..1db79f36de --- /dev/null +++ b/board/zoombini/build.mk @@ -0,0 +1,13 @@ +# -*- makefile -*- +# Copyright 2017 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=npcx +CHIP_FAMILY:=npcx7 +CHIP_VARIANT:=npcx7m6f + +board-y=battery.o board.o usb_pd_policy.o diff --git a/board/zoombini/ec.tasklist b/board/zoombini/ec.tasklist new file mode 100644 index 0000000000..4aae42a072 --- /dev/null +++ b/board/zoombini/ec.tasklist @@ -0,0 +1,35 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + * + * For USB PD tasks, IDs must be in consecutive order and correspond to + * the port which they are for. See TASK_ID_TO_PD_PORT() macro. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C2, pd_task, NULL, LARGER_TASK_STACK_SIZE) diff --git a/board/zoombini/gpio.inc b/board/zoombini/gpio.inc new file mode 100644 index 0000000000..5b022c45bc --- /dev/null +++ b/board/zoombini/gpio.inc @@ -0,0 +1,93 @@ +/* -*- mode:c -*- + * + * Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +GPIO_INT(USB_C0_PD_INT_L, PIN(6, 1), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C1_PD_INT_L, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C2_PD_INT_L, PIN(9, 5), GPIO_INT_FALLING, tcpc_alert_event) + +GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_button_interrupt) +GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH, lid_interrupt) +GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) + +/* Power Signals. */ +GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_SUS_L, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt) +/* TODO(aaboagye): Internal PU may be needed later on... */ +GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt) +/* TODO(aaboagye): is this the same as DSW_PWROK ? */ +GPIO_INT(PMIC_DPWROK, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) + +/* Power Enables. */ +GPIO(EN_PP3300_DSW, PIN(6, 0), GPIO_OUT_LOW) +GPIO(EN_PP3300_EC_TCPC_DX, PIN(8, 5), GPIO_OUT_HIGH) +GPIO(EN_PP3300_TRACKPAD, PIN(B, 7), GPIO_ODR_LOW) +GPIO(EN_PP3300_WLAN, PIN(C, 0), GPIO_ODR_LOW) +GPIO(EN_PP3300_WWAN, PIN(D, 7), GPIO_ODR_LOW) +GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW) + +GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) +GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) /* Case Closed Debug mode. */ +GPIO(KB_BL_EN, PIN(8, 6), GPIO_OUT_LOW) + +GPIO(PCH_DSW_PWROK, PIN(3, 7), GPIO_OUT_LOW) /* EC_PCH_DSW_PWROK */ +/* TODO(aaboagye): Revisit these default states. */ +GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* EC_PCH_RSMRST_L */ +GPIO(PCH_RTCRST, PIN(7, 6), GPIO_OUT_LOW) /* EC_PCH_RTCRST */ +GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ +GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_OUT_HIGH) /* EC_PCH_WAKE_ODL */ +GPIO(CPU_PROCHOT, PIN(3, 4), GPIO_INPUT) /* PCH_PROCHOT_ODL */ +GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) +GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) +GPIO(I2C1_SCL, PIN(9, 0), GPIO_INPUT) +GPIO(I2C1_SDA, PIN(8, 7), GPIO_INPUT) +GPIO(I2C2_SCL, PIN(9, 2), GPIO_INPUT) +GPIO(I2C2_SDA, PIN(9, 1), GPIO_INPUT) +GPIO(I2C3_SCL, PIN(D, 1), GPIO_INPUT) +GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT) +GPIO(I2C5_SCL, PIN(3, 3), GPIO_INPUT) +GPIO(I2C5_SDA, PIN(3, 6), GPIO_INPUT) + +GPIO(BAT_PRESENT_L, PIN(E, 5), GPIO_INPUT) +GPIO(USB_PD_RST_L, PIN(F, 1), GPIO_ODR_HIGH) + +GPIO(USB_C0_5V_EN, PIN(6, 7), GPIO_OUT_LOW) +GPIO(USB_C1_5V_EN, PIN(7, 0), GPIO_OUT_LOW) +GPIO(USB_C2_5V_EN, PIN(6, 3), GPIO_OUT_LOW) + +GPIO(USB_C0_CHARGE_EN_L, PIN(0, 3), GPIO_OUT_LOW) +GPIO(USB_C1_CHARGE_EN_L, PIN(0, 4), GPIO_OUT_LOW) +GPIO(USB_C2_CHARGE_EN_L, PIN(4, 0), GPIO_OUT_LOW) + +/* UART Pins */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, GPIO_PULL_UP) +/* I2C Ports */ +ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, GPIO_PULL_UP) /* I2C0 */ +ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, GPIO_PULL_UP) /* I2C1 SDA / I2C2 */ +ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, GPIO_PULL_UP) /* I2C1 SCL */ +ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, GPIO_PULL_UP) /* I2C3 */ +ALTERNATE(PIN_MASK(3, 0x44), 1, MODULE_I2C, GPIO_PULL_UP) /* I2C5 */ + +/* Keyboard Pins */ +/* KSI_00-01 */ +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) +/* KSI_02-07 */ +ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) +/* KSO_00-01 */ +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) +/* KSO_02 inverted */ +GPIO(KBD_KSO2, PIN(1, 7), GPIO_ODR_LOW) +/* KSO_03-09 */ +ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) +/* KSO_10-12 */ +ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) diff --git a/board/zoombini/usb_pd_policy.c b/board/zoombini/usb_pd_policy.c new file mode 100644 index 0000000000..6f035832f8 --- /dev/null +++ b/board/zoombini/usb_pd_policy.c @@ -0,0 +1,413 @@ +/* Copyright 2017 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "charge_manager.h" +#include "common.h" +#include "console.h" +#include "compile_time_macros.h" +#include "ec_commands.h" +#include "gpio.h" +#include "system.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "util.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_COMM_CAP|\ + PDO_FIXED_DATA_SWAP) + +/* TODO(aaboagye): Determine correct values. */ +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +/* TODO(aaboagye): Determine correct values. */ +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* Allow data swap if we are a UFP, otherwise don't allow. */ + return (data_role == PD_ROLE_UFP) ? 1 : 0; +} + +void pd_check_dr_role(int port, int dr_role, int flags) +{ + /* If UFP, try to switch to DFP */ + if ((flags & PD_FLAGS_PARTNER_DR_DATA) && + dr_role == PD_ROLE_UFP && + system_get_image_copy() != SYSTEM_IMAGE_RO) + pd_request_data_swap(port); +} + +/* TODO(aaboagye): re-eval for 3.0 & FRS. */ +int pd_check_power_swap(int port) +{ + /* + * Allow power swap as long as we are acting as a dual role device, + * otherwise assume our role is fixed (not in S0 or console command + * to fix our role). + */ + return pd_get_dual_role() == PD_DRP_TOGGLE_ON ? 1 : 0; +} + +void pd_check_pr_role(int port, int pr_role, int flags) +{ + /* + * If partner is dual-role power and dualrole toggling is on, consider + * if a power swap is necessary. + */ + if ((flags & PD_FLAGS_PARTNER_DR_POWER) && + pd_get_dual_role() == PD_DRP_TOGGLE_ON) { + /* + * If we are a sink and partner is not externally powered, then + * swap to become a source. If we are source and partner is + * externally powered, swap to become a sink. + */ + int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER; + + if ((!partner_extpower && pr_role == PD_ROLE_SINK) || + (partner_extpower && pr_role == PD_ROLE_SOURCE)) + pd_request_power_swap(port); + } +} + +int pd_check_vconn_swap(int port) +{ + /* In G3, do not allow VCONN swap since PP5000_A rail is off. */ + return gpio_get_level(GPIO_PCH_SLP_SUS_L); +} + +void pd_execute_data_swap(int port, int data_role) +{ + /* Do nothing */ +} + +int pd_is_valid_input_voltage(int mv) +{ + return 1; +} + +void pd_power_supply_reset(int port) +{ + /* Disable VBUS. */ + switch (port) { + case 0: + gpio_set_level(GPIO_USB_C0_5V_EN, 0); + break; + + case 1: + gpio_set_level(GPIO_USB_C1_5V_EN, 0); + break; + + case 2: + gpio_set_level(GPIO_USB_C2_5V_EN, 0); + break; + + default: + return; + }; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +void pd_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ + struct charge_port_info charge; + + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_PD, port, &charge); +} + +int pd_set_power_supply_ready(int port) +{ + switch (port) { + case 0: + /* Disable charging. */ + gpio_set_level(GPIO_USB_C0_CHARGE_EN_L, 1); + + /* Provide VBUS. */ + gpio_set_level(GPIO_USB_C0_5V_EN, 1); + + break; + + case 1: + /* Disable charging. */ + gpio_set_level(GPIO_USB_C1_CHARGE_EN_L, 1); + + /* Provide VBUS. */ + gpio_set_level(GPIO_USB_C1_5V_EN, 1); + + break; + + case 2: + /* Disable charging. */ + gpio_set_level(GPIO_USB_C2_CHARGE_EN_L, 1); + + /* Provide VBUS. */ + gpio_set_level(GPIO_USB_C2_5V_EN, 1); + + break; + + default: + break; + }; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +void typec_set_input_current_limit(int port, uint32_t max_ma, + uint32_t supply_voltage) +{ + struct charge_port_info charge; + + charge.current = max_ma; + charge.voltage = supply_voltage; + charge_manager_update_charge(CHARGE_SUPPLIER_TYPEC, port, &charge); +} + +/* ----------------- Vendor Defined Messages ------------------ */ +const struct svdm_response svdm_rsp = { + .identity = NULL, + .svids = NULL, + .modes = NULL, +}; + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + int cmd = PD_VDO_CMD(payload[0]); + uint16_t dev_id = 0; + int is_rw, is_latest; + + /* make sure we have some payload */ + if (cnt == 0) + return 0; + + switch (cmd) { + case VDO_CMD_VERSION: + /* guarantee last byte of payload is null character */ + *(payload + cnt - 1) = 0; + CPRINTF("version: %s\n", (char *)(payload+1)); + break; + case VDO_CMD_READ_INFO: + case VDO_CMD_SEND_INFO: + /* copy hash */ + if (cnt == 7) { + dev_id = VDO_INFO_HW_DEV_ID(payload[6]); + is_rw = VDO_INFO_IS_RW(payload[6]); + + is_latest = pd_dev_store_rw_hash(port, + dev_id, + payload + 1, + is_rw ? + SYSTEM_IMAGE_RW : + SYSTEM_IMAGE_RO); + + /* + * Send update host event unless our RW hash is + * already known to be the latest update RW. + */ + if (!is_rw || !is_latest) + pd_send_host_event(PD_EVENT_UPDATE_DEVICE); + + CPRINTF("DevId:%d.%d SW:%d RW:%d\n", + HW_DEV_ID_MAJ(dev_id), + HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), + is_rw); + } else if (cnt == 6) { + /* really old devices don't have last byte */ + pd_dev_store_rw_hash(port, dev_id, payload + 1, + SYSTEM_IMAGE_UNKNOWN); + } + break; + case VDO_CMD_CURRENT: + CPRINTF("Current: %dmA\n", payload[1]); + break; + case VDO_CMD_FLIP: + usb_mux_flip(port); + break; +#ifdef CONFIG_USB_PD_LOGGING + case VDO_CMD_GET_LOG: + pd_log_recv_vdm(port, cnt, payload); + break; +#endif /* CONFIG_USB_PD_LOGGING */ + } + + return 0; +} + +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +static int dp_flags[CONFIG_USB_PD_PORT_COUNT]; +static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT]; + +static void svdm_safe_dp_mode(int port) +{ + /* make DP interface safe until configure */ + dp_flags[port] = 0; + dp_status[port] = 0; + usb_mux_set(port, TYPEC_MUX_NONE, + USB_SWITCH_CONNECT, pd_get_polarity(port)); +} + +static int svdm_enter_dp_mode(int port, uint32_t mode_caps) +{ + /* Only enter mode if device is DFP_D capable */ + if (mode_caps & MODE_DP_SNK) { + svdm_safe_dp_mode(port); + return 0; + } + + return -1; +} + +static int svdm_dp_status(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_STATUS | VDO_OPOS(opos)); + payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON)), + 0, /* power low? ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON))); + return 2; +}; + +static int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); + int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); + + if (!pin_mode) + return 0; + + usb_mux_set(port, mf_pref ? TYPEC_MUX_DOCK : TYPEC_MUX_DP, + USB_SWITCH_CONNECT, pd_get_polarity(port)); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +static void svdm_dp_post_config(int port) +{ + const struct usb_mux *mux = &usb_muxes[port]; + + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; + mux->hpd_update(port, 1, 0); +} + +static int svdm_dp_attention(int port, uint32_t *payload) +{ + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + const struct usb_mux *mux = &usb_muxes[port]; + + dp_status[port] = payload[1]; + if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { + if (lvl) + dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; + return 1; + } + mux->hpd_update(port, lvl, irq); + + /* ack */ + return 1; +} + +static void svdm_exit_dp_mode(int port) +{ + const struct usb_mux *mux = &usb_muxes[port]; + + svdm_safe_dp_mode(port); + mux->hpd_update(port, 0, 0); +} + +static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) +{ + /* Always enter GFU mode */ + return 0; +} + +static void svdm_exit_gfu_mode(int port) +{ +} + +static int svdm_gfu_status(int port, uint32_t *payload) +{ + /* + * This is called after enter mode is successful, send unstructured + * VDM to read info. + */ + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0); + return 0; +} + +static int svdm_gfu_config(int port, uint32_t *payload) +{ + return 0; +} + +static int svdm_gfu_attention(int port, uint32_t *payload) +{ + return 0; +} + +const struct svdm_amode_fx supported_modes[] = { + { + .svid = USB_SID_DISPLAYPORT, + .enter = &svdm_enter_dp_mode, + .status = &svdm_dp_status, + .config = &svdm_dp_config, + .post_config = &svdm_dp_post_config, + .attention = &svdm_dp_attention, + .exit = &svdm_exit_dp_mode, + }, + { + .svid = USB_VID_GOOGLE, + .enter = &svdm_enter_gfu_mode, + .status = &svdm_gfu_status, + .config = &svdm_gfu_config, + .attention = &svdm_gfu_attention, + .exit = &svdm_exit_gfu_mode, + } +}; +const int supported_modes_cnt = ARRAY_SIZE(supported_modes); +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/include/config.h b/include/config.h index 8e7bb679f1..9421cb4a81 100644 --- a/include/config.h +++ b/include/config.h @@ -2050,21 +2050,14 @@ /* Define the SPI port to use to access the flash */ #undef CONFIG_SPI_FLASH_PORT -/* Support W25Q40 SPI flash */ +/* Select any of the following SPI flash configs that your board uses. */ +#undef CONFIG_SPI_FLASH_GD25LQ40 +#undef CONFIG_SPI_FLASH_GD25Q41B #undef CONFIG_SPI_FLASH_W25Q40 - -/* Support W25Q64 SPI flash */ #undef CONFIG_SPI_FLASH_W25Q64 - -/* Support W25X40 SPI flash */ +#undef CONFIG_SPI_FLASH_W25Q80 #undef CONFIG_SPI_FLASH_W25X40 -/* Support GD25Q40 SPI flash */ -#undef CONFIG_SPI_FLASH_GD25LQ40 - -/* Support GD25Q41B SPI flash */ -#undef CONFIG_SPI_FLASH_GD25Q41B - /* SPI flash part supports SR2 register */ #undef CONFIG_SPI_FLASH_HAS_SR2 -- cgit v1.2.1