From fa17d634d2bd6be222ce4652285f38ab626e5779 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 5 Apr 2019 10:19:30 -0600 Subject: Zork/Trembyle: initial setup Create Zork baseboard and Trembyle mainboard based on Grunt. Currently, these are a copy of Grunt with the names and copyright dates updated, and will be modified with Trembyle specific settings later. BUG=b:129697474 TEST=make BOARD=trembyle BRANCH=None Change-Id: Ice2e7943d0c013e81ccc4f84ca98c3c6fe1bf4b1 Signed-off-by: Martin Roth Reviewed-on: https://chromium-review.googlesource.com/1554840 Commit-Ready: ChromeOS CL Exonerator Bot Legacy-Commit-Queue: Commit Bot Reviewed-by: Diana Z Reviewed-by: Edward Hill --- baseboard/zork/analyzestack.yaml | 2 + baseboard/zork/baseboard.c | 602 +++++++++++++++++++++++++++++++++++++++ baseboard/zork/baseboard.h | 255 +++++++++++++++++ baseboard/zork/build.mk | 10 + baseboard/zork/usb_pd_policy.c | 452 +++++++++++++++++++++++++++++ board/trembyle/analyzestack.yaml | 1 + board/trembyle/battery.c | 65 +++++ board/trembyle/board.c | 249 ++++++++++++++++ board/trembyle/board.h | 83 ++++++ board/trembyle/build.mk | 15 + board/trembyle/ec.tasklist | 26 ++ board/trembyle/gpio.inc | 115 ++++++++ board/trembyle/led.c | 66 +++++ 13 files changed, 1941 insertions(+) create mode 100644 baseboard/zork/analyzestack.yaml create mode 100644 baseboard/zork/baseboard.c create mode 100644 baseboard/zork/baseboard.h create mode 100644 baseboard/zork/build.mk create mode 100644 baseboard/zork/usb_pd_policy.c create mode 120000 board/trembyle/analyzestack.yaml create mode 100644 board/trembyle/battery.c create mode 100644 board/trembyle/board.c create mode 100644 board/trembyle/board.h create mode 100644 board/trembyle/build.mk create mode 100644 board/trembyle/ec.tasklist create mode 100644 board/trembyle/gpio.inc create mode 100644 board/trembyle/led.c diff --git a/baseboard/zork/analyzestack.yaml b/baseboard/zork/analyzestack.yaml new file mode 100644 index 0000000000..7ff5f39644 --- /dev/null +++ b/baseboard/zork/analyzestack.yaml @@ -0,0 +1,2 @@ +remove: +- panic_assert_fail diff --git a/baseboard/zork/baseboard.c b/baseboard/zork/baseboard.c new file mode 100644 index 0000000000..36786ce34d --- /dev/null +++ b/baseboard/zork/baseboard.c @@ -0,0 +1,602 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zork family-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "button.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "charge_state_v2.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "cros_board_info.h" +#include "driver/accel_kionix.h" +#include "driver/accel_kx022.h" +#include "driver/accelgyro_bmi160.h" +#include "driver/bc12/max14637.h" +#include "driver/ppc/sn5s330.h" +#include "driver/tcpm/anx74xx.h" +#include "driver/tcpm/ps8xxx.h" +#include "driver/temp_sensor/sb_tsi.h" +#include "ec_commands.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "motion_sense.h" +#include "power.h" +#include "power_button.h" +#include "registers.h" +#include "switch.h" +#include "system.h" +#include "task.h" +#include "tcpci.h" +#include "temp_sensor.h" +#include "thermistor.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usb_pd_tcpm.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +const enum gpio_signal hibernate_wake_pins[] = { + GPIO_LID_OPEN, + GPIO_AC_PRESENT, + GPIO_POWER_BUTTON_L, +}; +const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); + +const struct adc_t adc_channels[] = { + [ADC_TEMP_SENSOR_CHARGER] = { + "CHARGER", NPCX_ADC_CH0, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, + [ADC_TEMP_SENSOR_SOC] = { + "SOC", NPCX_ADC_CH1, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, + [ADC_VBUS] = { + "VBUS", NPCX_ADC_CH8, ADC_MAX_VOLT*10, ADC_READ_MAX+1, 0 + }, + [ADC_SKU_ID1] = { + "SKU1", NPCX_ADC_CH9, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, + [ADC_SKU_ID2] = { + "SKU2", NPCX_ADC_CH4, ADC_MAX_VOLT, ADC_READ_MAX+1, 0 + }, +}; +BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT); + +/* Power signal list. Must match order of enum power_signal. */ +const struct power_signal_info power_signal_list[] = { + {GPIO_PCH_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S3_DEASSERTED"}, + {GPIO_PCH_SLP_S5_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_S5_DEASSERTED"}, + {GPIO_S0_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S0_PGOOD"}, + {GPIO_S5_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "S5_PGOOD"}, +}; +BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT); + +const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { + [USB_PD_PORT_ANX74XX] = { + .i2c_host_port = I2C_PORT_TCPC0, + .i2c_slave_addr = ANX74XX_I2C_ADDR1, + .drv = &anx74xx_tcpm_drv, + /* Alert is active-low, open-drain */ + .flags = TCPC_FLAGS_ALERT_OD, + }, + [USB_PD_PORT_PS8751] = { + .i2c_host_port = I2C_PORT_TCPC1, + .i2c_slave_addr = PS8751_I2C_ADDR1, + .drv = &ps8xxx_tcpm_drv, + /* Alert is active-low, push-pull */ + .flags = 0, + }, +}; + +void tcpc_alert_event(enum gpio_signal signal) +{ + int port = -1; + + switch (signal) { + case GPIO_USB_C0_PD_INT_ODL: + port = 0; + break; + case GPIO_USB_C1_PD_INT_ODL: + port = 1; + break; + default: + return; + } + + schedule_deferred_pd_interrupt(port); +} + +struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { + [USB_PD_PORT_ANX74XX] = { + .driver = &anx74xx_tcpm_usb_mux_driver, + .hpd_update = &anx74xx_tcpc_update_hpd_status, + }, + [USB_PD_PORT_PS8751] = { + .driver = &tcpci_tcpm_usb_mux_driver, + .hpd_update = &ps8xxx_tcpc_update_hpd_status, + /* TODO(ecgh): ps8751_tune_mux needed? */ + } +}; + +struct ppc_config_t ppc_chips[] = { + { + .i2c_port = I2C_PORT_TCPC0, + .i2c_addr = SN5S330_ADDR0, + .drv = &sn5s330_drv + }, + { + .i2c_port = I2C_PORT_TCPC1, + .i2c_addr = SN5S330_ADDR0, + .drv = &sn5s330_drv + }, +}; +unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); + +int ppc_get_alert_status(int port) +{ + if (port == 0) + return gpio_get_level(GPIO_USB_C0_SWCTL_INT_ODL) == 0; + else + return gpio_get_level(GPIO_USB_C1_SWCTL_INT_ODL) == 0; +} + + +/* BC 1.2 chip Configuration */ +const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_COUNT] = { + [USB_PD_PORT_ANX74XX] = { + .chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_L, + .chg_det_pin = GPIO_USB_C0_BC12_CHG_DET, + .flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW, + }, + [USB_PD_PORT_PS8751] = { + .chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_L, + .chg_det_pin = GPIO_USB_C1_BC12_CHG_DET, + .flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW, + }, +}; + +const int usb_port_enable[USB_PORT_COUNT] = { + GPIO_EN_USB_A0_5V, + GPIO_EN_USB_A1_5V, +}; + +static void baseboard_chipset_suspend(void) +{ + /* + * Turn off display backlight. This ensures that the backlight stays off + * in S3, no matter what the AP has it set to. The AP also controls it. + * This is here more for legacy reasons. + */ + gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend, + HOOK_PRIO_DEFAULT); + +static void baseboard_chipset_resume(void) +{ + /* Allow display backlight to turn on. See above backlight comment */ + gpio_set_level(GPIO_ENABLE_BACKLIGHT_L, 0); + +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT); + +static void baseboard_chipset_startup(void) +{ + /* + * Enable sensor power (lid accel, gyro) in S3 for calculating the lid + * angle (needed on convertibles to disable resume from keyboard in + * tablet mode). + */ + gpio_set_level(GPIO_EN_PP1800_SENSOR, 1); +} +DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup, + HOOK_PRIO_DEFAULT); + +static void baseboard_chipset_shutdown(void) +{ + /* Disable sensor power (lid accel, gyro) in S5. */ + gpio_set_level(GPIO_EN_PP1800_SENSOR, 0); +} +DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown, + HOOK_PRIO_DEFAULT); + +int board_is_i2c_port_powered(int port) +{ + if (port != I2C_PORT_SENSOR) + return 1; + + /* Sensor power (lid accel, gyro) is off in S5 (and G3). */ + return chipset_in_state(CHIPSET_STATE_ANY_OFF) ? 0 : 1; +} + +int board_set_active_charge_port(int port) +{ + int i; + + CPRINTS("New chg p%d", port); + + if (port == CHARGE_PORT_NONE) { + /* Disable all ports. */ + for (i = 0; i < ppc_cnt; i++) { + if (ppc_vbus_sink_enable(i, 0)) + CPRINTS("p%d: sink disable failed.", i); + } + + return EC_SUCCESS; + } + + /* Check if the port is sourcing VBUS. */ + if (ppc_is_sourcing_vbus(port)) { + CPRINTF("Skip enable p%d", port); + return EC_ERROR_INVAL; + } + + /* + * Turn off the other ports' sink path FETs, before enabling the + * requested charge port. + */ + for (i = 0; i < ppc_cnt; i++) { + if (i == port) + continue; + + if (ppc_vbus_sink_enable(i, 0)) + CPRINTS("p%d: sink disable failed.", i); + } + + /* Enable requested charge port. */ + if (ppc_vbus_sink_enable(port, 1)) { + CPRINTS("p%d: sink enable failed."); + return EC_ERROR_UNKNOWN; + } + + return EC_SUCCESS; +} + +void board_set_charge_limit(int port, int supplier, int charge_ma, + int max_ma, int charge_mv) +{ + /* + * Limit the input current to 95% negotiated limit, + * to account for the charger chip margin. + */ + charge_ma = charge_ma * 95 / 100; + charge_set_input_current_limit(MAX(charge_ma, + CONFIG_CHARGER_INPUT_CURRENT), + charge_mv); +} + +/* Keyboard scan setting */ +struct keyboard_scan_config keyscan_config = { + /* Extra delay when KSO2 is tied to Cr50. */ + .output_settle_us = 60, + .debounce_down_us = 6 * MSEC, + .debounce_up_us = 30 * MSEC, + .scan_period_us = 1500, + .min_post_scan_delay_us = 1000, + .poll_timeout_us = SECOND, + .actual_key_mask = { + 0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff, + 0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca /* full set */ + }, +}; + +/* + * We use 11 as the scaling factor so that the maximum mV value below (2761) + * can be compressed to fit in a uint8_t. + */ +#define THERMISTOR_SCALING_FACTOR 11 + +/* + * Values are calculated from the "Resistance VS. Temperature" table on the + * Murata page for part NCP15WB473F03RC. Vdd=3.3V, R=30.9Kohm. + */ +static const struct thermistor_data_pair thermistor_data[] = { + { 2761 / THERMISTOR_SCALING_FACTOR, 0}, + { 2492 / THERMISTOR_SCALING_FACTOR, 10}, + { 2167 / THERMISTOR_SCALING_FACTOR, 20}, + { 1812 / THERMISTOR_SCALING_FACTOR, 30}, + { 1462 / THERMISTOR_SCALING_FACTOR, 40}, + { 1146 / THERMISTOR_SCALING_FACTOR, 50}, + { 878 / THERMISTOR_SCALING_FACTOR, 60}, + { 665 / THERMISTOR_SCALING_FACTOR, 70}, + { 500 / THERMISTOR_SCALING_FACTOR, 80}, + { 434 / THERMISTOR_SCALING_FACTOR, 85}, + { 376 / THERMISTOR_SCALING_FACTOR, 90}, + { 326 / THERMISTOR_SCALING_FACTOR, 95}, + { 283 / THERMISTOR_SCALING_FACTOR, 100} +}; + +static const struct thermistor_info thermistor_info = { + .scaling_factor = THERMISTOR_SCALING_FACTOR, + .num_pairs = ARRAY_SIZE(thermistor_data), + .data = thermistor_data, +}; + +static int board_get_temp(int idx, int *temp_k) +{ + /* idx is the sensor index set below in temp_sensors[] */ + int mv = adc_read_channel( + idx ? ADC_TEMP_SENSOR_SOC : ADC_TEMP_SENSOR_CHARGER); + int temp_c; + + if (mv < 0) + return -1; + + temp_c = thermistor_linear_interpolate(mv, &thermistor_info); + *temp_k = C_TO_K(temp_c); + return 0; +} + +const struct temp_sensor_t temp_sensors[] = { + {"Charger", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 0, 1}, + {"SOC", TEMP_SENSOR_TYPE_BOARD, board_get_temp, 1, 5}, + {"CPU", TEMP_SENSOR_TYPE_CPU, sb_tsi_get_val, 0, 4}, +}; +BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT); + +#ifdef HAS_TASK_MOTIONSENSE + +/* Motion sensors */ +static struct mutex g_lid_mutex; +static struct mutex g_base_mutex; + +mat33_fp_t zork_base_standard_ref = { + { FLOAT_TO_FP(1), 0, 0}, + { 0, FLOAT_TO_FP(1), 0}, + { 0, 0, FLOAT_TO_FP(1)} +}; + +mat33_fp_t lid_standard_ref = { + { FLOAT_TO_FP(1), 0, 0}, + { 0, FLOAT_TO_FP(1), 0}, + { 0, 0, FLOAT_TO_FP(1)} +}; + +/* sensor private data */ +static struct kionix_accel_data g_kx022_data; +static struct bmi160_drv_data_t g_bmi160_data; + +/* TODO(gcc >= 5.0) Remove the casts to const pointer at rot_standard_ref */ +struct motion_sensor_t motion_sensors[] = { + [LID_ACCEL] = { + .name = "Lid Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_KX022, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_LID, + .drv = &kionix_accel_drv, + .mutex = &g_lid_mutex, + .drv_data = &g_kx022_data, + .port = I2C_PORT_SENSOR, + .addr = KX022_ADDR1, + .rot_standard_ref = (const mat33_fp_t *)&lid_standard_ref, + .default_range = 2, /* g, enough for laptop. */ + .min_frequency = KX022_ACCEL_MIN_FREQ, + .max_frequency = KX022_ACCEL_MAX_FREQ, + .config = { + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100, + }, + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + }, + }, + }, + + [BASE_ACCEL] = { + .name = "Base Accel", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMI160, + .type = MOTIONSENSE_TYPE_ACCEL, + .location = MOTIONSENSE_LOC_BASE, + .drv = &bmi160_drv, + .mutex = &g_base_mutex, + .drv_data = &g_bmi160_data, + .port = I2C_PORT_SENSOR, + .addr = BMI160_ADDR0, + .default_range = 2, /* g, enough for laptop */ + .rot_standard_ref = (const mat33_fp_t *)&zork_base_standard_ref, + .min_frequency = BMI160_ACCEL_MIN_FREQ, + .max_frequency = BMI160_ACCEL_MAX_FREQ, + .config = { + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S0] = { + .odr = 10000 | ROUND_UP_FLAG, + .ec_rate = 100, + }, + /* EC use accel for angle detection */ + [SENSOR_CONFIG_EC_S3] = { + .odr = 10000 | ROUND_UP_FLAG, + }, + }, + }, + + [BASE_GYRO] = { + .name = "Base Gyro", + .active_mask = SENSOR_ACTIVE_S0_S3, + .chip = MOTIONSENSE_CHIP_BMI160, + .type = MOTIONSENSE_TYPE_GYRO, + .location = MOTIONSENSE_LOC_BASE, + .drv = &bmi160_drv, + .mutex = &g_base_mutex, + .drv_data = &g_bmi160_data, + .port = I2C_PORT_SENSOR, + .addr = BMI160_ADDR0, + .default_range = 1000, /* dps */ + .rot_standard_ref = (const mat33_fp_t *)&zork_base_standard_ref, + .min_frequency = BMI160_GYRO_MIN_FREQ, + .max_frequency = BMI160_GYRO_MAX_FREQ, + }, +}; + +unsigned int motion_sensor_count = ARRAY_SIZE(motion_sensors); + +#endif /* HAS_TASK_MOTIONSENSE */ + +#ifndef TEST_BUILD +void lid_angle_peripheral_enable(int enable) +{ + if (board_is_convertible()) + keyboard_scan_enable(enable, KB_SCAN_DISABLE_LID_ANGLE); +} +#endif + +static const int sku_thresh_mv[] = { + /* Vin = 3.3V, Ideal voltage, R2 values listed below */ + /* R1 = 51.1 kOhm */ + 200, /* 124 mV, 2.0 Kohm */ + 366, /* 278 mV, 4.7 Kohm */ + 550, /* 456 mV, 8.2 Kohm */ + 752, /* 644 mV, 12.4 Kohm */ + 927, /* 860 mV, 18.0 Kohm */ + 1073, /* 993 mV, 22.0 Kohm */ + 1235, /* 1152 mV, 27.4 Kohm */ + 1386, /* 1318 mV, 34.0 Kohm */ + 1552, /* 1453 mV, 40.2 Kohm */ + /* R1 = 10.0 kOhm */ + 1739, /* 1650 mV, 10.0 Kohm */ + 1976, /* 1827 mV, 12.4 Kohm */ + 2197, /* 2121 mV, 18.0 Kohm */ + 2344, /* 2269 mV, 22.0 Kohm */ + 2484, /* 2418 mV, 27.4 Kohm */ + 2636, /* 2550 mV, 34.0 Kohm */ + 2823, /* 2721 mV, 47.0 Kohm */ +}; + +static int board_read_sku_adc(enum adc_channel chan) +{ + int mv; + int i; + + mv = adc_read_channel(chan); + + if (mv == ADC_READ_ERROR) + return -1; + + for (i = 0; i < ARRAY_SIZE(sku_thresh_mv); i++) + if (mv < sku_thresh_mv[i]) + return i; + + return -1; +} + +static uint32_t board_get_adc_sku_id(void) +{ + int sku_id1, sku_id2; + + sku_id1 = board_read_sku_adc(ADC_SKU_ID1); + sku_id2 = board_read_sku_adc(ADC_SKU_ID2); + + if (sku_id1 < 0 || sku_id2 < 0) + return 0; + + return (sku_id2 << 4) | sku_id1; +} + +static int board_get_gpio_board_version(void) +{ + return + (!!gpio_get_level(GPIO_BOARD_VERSION1) << 0) | + (!!gpio_get_level(GPIO_BOARD_VERSION2) << 1) | + (!!gpio_get_level(GPIO_BOARD_VERSION3) << 2); +} + +static int board_version; +static uint32_t sku_id; + +static void cbi_init(void) +{ + board_version = board_get_gpio_board_version(); + sku_id = board_get_adc_sku_id(); + + /* + * Use board version and SKU ID from CBI EEPROM if the board supports + * it and the SKU ID set via resistors + ADC is not valid. + */ +#ifdef CONFIG_CROS_BOARD_INFO + if (sku_id == 0 || sku_id == 0xff) { + uint32_t val; + + if (cbi_get_board_version(&val) == EC_SUCCESS) + board_version = val; + if (cbi_get_sku_id(&val) == EC_SUCCESS) + sku_id = val; + } +#endif + +#ifdef HAS_TASK_MOTIONSENSE + board_update_sensor_config_from_sku(); +#endif + + ccprints("Board Version: %d (0x%x)", board_version, board_version); + ccprints("SKU: %d (0x%x)", sku_id, sku_id); +} +/* + * Reading the SKU resistors requires the ADC module. If we are using EEPROM + * then we also need the I2C module, but that is available before ADC. + */ +DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_ADC + 1); + +uint32_t system_get_sku_id(void) +{ + return sku_id; +} + +int board_get_version(void) +{ + return board_version; +} + +/* + * Returns 1 for boards that are convertible into tablet mode, and zero for + * clamshells. + */ +int board_is_convertible(void) +{ + /* TODO: Add convertible SKU values */ + return 0; +} + +int board_is_lid_angle_tablet_mode(void) +{ + return board_is_convertible(); +} + +uint32_t board_override_feature_flags0(uint32_t flags0) +{ + return flags0; +} + +uint32_t board_override_feature_flags1(uint32_t flags1) +{ + return flags1; +} + +void board_hibernate(void) +{ + /* + * Some versions of some boards keep the port 0 PPC powered on while + * the EC hibernates (so Closed Case Debugging keeps working). + * Make sure the source FET is off and turn on the sink FET, so that + * plugging in AC will wake the EC. This matches the dead-battery + * behavior of the powered off PPC. + */ + ppc_vbus_source_enable(0, 0); + ppc_vbus_sink_enable(0, 1); +} diff --git a/baseboard/zork/baseboard.h b/baseboard/zork/baseboard.h new file mode 100644 index 0000000000..2320450b75 --- /dev/null +++ b/baseboard/zork/baseboard.h @@ -0,0 +1,255 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zork family-specific configuration */ + +#ifndef __CROS_EC_BASEBOARD_H +#define __CROS_EC_BASEBOARD_H + +/* NPCX7 config */ +#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ +#define NPCX_TACH_SEL2 0 /* No tach. */ +#define NPCX7_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ + +/* Internal SPI flash on NPCX7 */ +/* Flash is 1MB but reserve half for future use. */ +#define CONFIG_FLASH_SIZE (512 * 1024) +#define CONFIG_SPI_FLASH_REGS +#define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */ + +/* + * Enable 1 slot of secure temporary storage to support + * suspend/resume with read/write memory training. + */ +#define CONFIG_VSTORE +#define CONFIG_VSTORE_SLOT_COUNT 1 + +#define CONFIG_ADC +#define CONFIG_BACKLIGHT_LID +#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW +#define CONFIG_BOARD_VERSION_CUSTOM +#define CONFIG_CMD_AP_RESET_LOG +#define CONFIG_EC_FEATURE_BOARD_OVERRIDE +#define CONFIG_HIBERNATE_PSL +#define CONFIG_HOSTCMD_LPC +#define CONFIG_HOSTCMD_SKUID +#define CONFIG_I2C +#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED +#define CONFIG_I2C_MASTER +#define CONFIG_LOW_POWER_IDLE +#define CONFIG_LOW_POWER_S0 +#define CONFIG_LTO +#define CONFIG_PWM +#define CONFIG_PWM_KBLIGHT +#define CONFIG_TEMP_SENSOR +#define CONFIG_THERMISTOR_NCP15WB +#define CONFIG_VBOOT_HASH +#define CONFIG_VOLUME_BUTTONS + +#define CONFIG_BATTERY_CUT_OFF +#define CONFIG_BATTERY_FUEL_GAUGE +#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_L +#define CONFIG_BATTERY_REVIVE_DISCONNECT +#define CONFIG_BATTERY_SMART + +#define CONFIG_BC12_DETECT_MAX14637 +#define CONFIG_CHARGER +#define CONFIG_CHARGER_V2 +#define CONFIG_CHARGE_MANAGER +#define CONFIG_CHARGER_DISCHARGE_ON_AC + +/* + * This limit impairs compatibility with BC1.2 chargers that are not actually + * capable of supplying 500 mA of current. When the charger is paralleled with + * the battery, raising this limit allows the power system to draw more current + * from the charger during startup. This improves compatibility with system + * batteries that may become excessively imbalanced after extended periods of + * rest. + * + * See also b/111214767 + */ +#define CONFIG_CHARGER_INPUT_CURRENT 512 +#define CONFIG_CHARGER_ISL9238 +#define CONFIG_CHARGER_SENSE_RESISTOR 10 +#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 +#define CONFIG_CHARGE_RAMP_HW +#define CONFIG_USB_CHARGER + +#define CONFIG_CHIPSET_STONEY +#define CONFIG_CHIPSET_RESET_HOOK +/* + * ACOK from ISL9238 sometimes has a negative pulse after connecting + * USB-C power. We want to ignore it. b/77455171 + */ +#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#define CONFIG_EXTPOWER_DEBOUNCE_MS 200 +#define CONFIG_EXTPOWER_GPIO +#define CONFIG_POWER_COMMON +#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5 +#define CONFIG_POWER_BUTTON +#define CONFIG_POWER_BUTTON_X86 + +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. If we add a delay between reset (1) + * and configuring GPIO output levels, then reset (2) will happen before the + * end of the delay so we avoid extra output toggles. + */ +#define CONFIG_GPIO_INIT_POWER_ON_DELAY_MS 100 + +#define CONFIG_KEYBOARD_BOARD_CONFIG +#define CONFIG_KEYBOARD_COL2_INVERTED +#define CONFIG_KEYBOARD_PROTOCOL_8042 + +#define CONFIG_USB_POWER_DELIVERY +#define CONFIG_CMD_PD_CONTROL +#define CONFIG_USB_PD_ALT_MODE +#define CONFIG_USB_PD_ALT_MODE_DFP +#define CONFIG_USB_PD_COMM_LOCKED +#define CONFIG_USB_PD_DISCHARGE_PPC +#define CONFIG_USB_PD_DUAL_ROLE +#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE +#define CONFIG_USB_PD_LOGGING +#define CONFIG_USB_PD_PORT_COUNT 2 +#define CONFIG_USB_PD_TCPC_LOW_POWER +#define CONFIG_USB_PD_TCPM_ANX3429 +#define CONFIG_USB_PD_TCPM_MUX +#define CONFIG_USB_PD_TCPM_PS8751 +#define CONFIG_USB_PD_TCPM_TCPCI +#define CONFIG_USB_PD_TRY_SRC +#define CONFIG_USB_PD_VBUS_DETECT_PPC +#define CONFIG_USBC_PPC_SN5S330 +#define CONFIG_USBC_PPC_DEDICATED_INT +#define CONFIG_USBC_SS_MUX +#define CONFIG_USBC_SS_MUX_DFP_ONLY +#define CONFIG_USBC_VCONN +#define CONFIG_USBC_VCONN_SWAP + +/* USB-A config */ +#define CONFIG_USB_PORT_POWER_DUMB +#define USB_PORT_COUNT 2 + +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */ +#define PD_VCONN_SWAP_DELAY 5000 /* us */ + +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_POWER_MW 45000 +#define PD_MAX_CURRENT_MA 3000 +#define PD_MAX_VOLTAGE_MV 20000 + +/* + * Minimum conditions to start AP and perform swsync. Note that when the + * charger is connected via USB-PD analog signaling, the boot will proceed + * regardless. + */ +#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 3 + +/* + * Require PD negotiation to be complete when we are in a low-battery condition + * prior to releasing depthcharge to the kernel. + */ +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW 15001 +#define CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT 3 + +/* Increase length of history buffer for port80 messages. */ +#undef CONFIG_PORT80_HISTORY_LEN +#define CONFIG_PORT80_HISTORY_LEN 256 + +#define I2C_PORT_BATTERY I2C_PORT_POWER +#define I2C_PORT_CHARGER I2C_PORT_POWER +#define I2C_PORT_POWER NPCX_I2C_PORT0_0 +#define I2C_PORT_TCPC0 NPCX_I2C_PORT1_0 +#define I2C_PORT_TCPC1 NPCX_I2C_PORT2_0 +#define I2C_PORT_THERMAL NPCX_I2C_PORT3_0 +#define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 +/* Accelerometer and Gyroscope are the same device. */ +#define I2C_PORT_ACCEL I2C_PORT_SENSOR + +/* Sensors */ +#define CONFIG_MKBP_EVENT +#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT + +/* Thermal */ +#define CONFIG_TEMP_SENSOR_SB_TSI + +/* FIFO size is a power of 2. */ +#define CONFIG_ACCEL_FIFO 256 + +/* Depends on how fast the AP boots and typical ODRs. */ +#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO / 3) + +#define USB_PD_PORT_ANX74XX 0 +#define USB_PD_PORT_PS8751 1 + +#ifndef __ASSEMBLER__ + +#include "gpio_signal.h" +#include "math_util.h" +#include "registers.h" + +enum adc_channel { + ADC_TEMP_SENSOR_CHARGER, + ADC_TEMP_SENSOR_SOC, + ADC_VBUS, + ADC_SKU_ID1, + ADC_SKU_ID2, + ADC_CH_COUNT +}; + +enum power_signal { + X86_SLP_S3_N, + X86_SLP_S5_N, + X86_S0_PGOOD, + X86_S5_PGOOD, + POWER_SIGNAL_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_CHARGER = 0, + TEMP_SENSOR_SOC, + TEMP_SENSOR_CPU, + TEMP_SENSOR_COUNT +}; + +enum sensor_id { + LID_ACCEL, + BASE_ACCEL, + BASE_GYRO, +}; + +/* + * Matrix to rotate accelerators into the standard reference frame. The default + * is the identity which is correct for the reference design. Variations of + * Zork may need to change it for manufacturability. + * For the lid: + * +x to the right + * +y up + * +z out of the page + * + * The principle axes of the body are aligned with the lid when the lid is in + * the 180 degree position (open, flat). + * + * Boards within the Zork family may need to modify this definition at + * board_init() time. + */ +extern mat33_fp_t zork_base_standard_ref; + +/* Sensors without hardware FIFO are in forced mode */ +#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL) + +void board_reset_pd_mcu(void); + +/* Common definition for the USB PD interrupt handlers. */ +void tcpc_alert_event(enum gpio_signal signal); + +int board_get_version(void); +int board_is_convertible(void); +void board_update_sensor_config_from_sku(void); + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BASEBOARD_H */ diff --git a/baseboard/zork/build.mk b/baseboard/zork/build.mk new file mode 100644 index 0000000000..c8ae965325 --- /dev/null +++ b/baseboard/zork/build.mk @@ -0,0 +1,10 @@ +# -*- makefile -*- +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Baseboard specific files build +# + +baseboard-y=baseboard.o +baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o diff --git a/baseboard/zork/usb_pd_policy.c b/baseboard/zork/usb_pd_policy.c new file mode 100644 index 0000000000..89be349157 --- /dev/null +++ b/baseboard/zork/usb_pd_policy.c @@ -0,0 +1,452 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shared USB-C policy for Zork boards */ + +#include "charge_manager.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "ec_commands.h" +#include "gpio.h" +#include "system.h" +#include "usb_mux.h" +#include "usb_pd.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) + +#define PDO_FIXED_FLAGS (PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP |\ + PDO_FIXED_COMM_CAP) + +const uint32_t pd_src_pdo[] = { + PDO_FIXED(5000, 1500, PDO_FIXED_FLAGS), +}; +const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo); + +const uint32_t pd_snk_pdo[] = { + PDO_FIXED(5000, 500, PDO_FIXED_FLAGS), + PDO_BATT(4750, 21000, 15000), + PDO_VAR(4750, 21000, 3000), +}; +const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo); + +int pd_board_checks(void) +{ + return EC_SUCCESS; +} + +int pd_check_data_swap(int port, int data_role) +{ + /* + * Allow data swap if we are a UFP, otherwise don't allow. + * + * When we are still in the Read-Only firmware, avoid swapping roles + * so we don't jump in RW as a SNK/DFP and potentially confuse the + * power supply by sending a soft-reset with wrong data role. + */ + return (data_role == PD_ROLE_UFP) && + (system_get_image_copy() != SYSTEM_IMAGE_RO) ? 1 : 0; +} + +void pd_check_dr_role(int port, int dr_role, int flags) +{ + /* If UFP, try to switch to DFP */ + if ((flags & PD_FLAGS_PARTNER_DR_DATA) && + dr_role == PD_ROLE_UFP && + system_get_image_copy() != SYSTEM_IMAGE_RO) + pd_request_data_swap(port); +} + +int pd_check_power_swap(int port) +{ + /* + * Allow power swap as long as we are acting as a dual role device, + * otherwise assume our role is fixed (not in S0 or console command + * to fix our role). + */ + return pd_get_dual_role(port) == PD_DRP_TOGGLE_ON ? 1 : 0; +} + +void pd_check_pr_role(int port, int pr_role, int flags) +{ + /* + * If partner is dual-role power and dualrole toggling is on, consider + * if a power swap is necessary. + */ + if ((flags & PD_FLAGS_PARTNER_DR_POWER) && + pd_get_dual_role(port) == PD_DRP_TOGGLE_ON) { + /* + * If we are a sink and partner is not externally powered, then + * swap to become a source. If we are source and partner is + * externally powered, swap to become a sink. + */ + int partner_extpower = flags & PD_FLAGS_PARTNER_EXTPOWER; + + if ((!partner_extpower && pr_role == PD_ROLE_SINK) || + (partner_extpower && pr_role == PD_ROLE_SOURCE)) + pd_request_power_swap(port); + } +} + +int pd_check_vconn_swap(int port) +{ + /* in G3, do not allow vconn swap since 5V rail is off */ + return gpio_get_level(GPIO_S5_PGOOD); +} + +void pd_execute_data_swap(int port, int data_role) +{ + /* Do nothing */ +} + +int pd_is_valid_input_voltage(int mv) +{ + return 1; +} + +void pd_power_supply_reset(int port) +{ + int prev_en; + + prev_en = ppc_is_sourcing_vbus(port); + + /* Disable VBUS. */ + ppc_vbus_source_enable(port, 0); + + /* Enable discharge if we were previously sourcing 5V */ + if (prev_en) + pd_set_vbus_discharge(port, 1); + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); +} + +int pd_set_power_supply_ready(int port) +{ + int rv; + + /* Disable charging. */ + rv = ppc_vbus_sink_enable(port, 0); + if (rv) + return rv; + + pd_set_vbus_discharge(port, 0); + + /* Provide Vbus. */ + rv = ppc_vbus_source_enable(port, 1); + if (rv) + return rv; + + /* Notify host of power info change. */ + pd_send_host_event(PD_EVENT_POWER_CHANGE); + + return EC_SUCCESS; +} + +void pd_transition_voltage(int idx) +{ + /* No-operation: we are always 5V */ +} + +int pd_snk_is_vbus_provided(int port) +{ + return ppc_is_vbus_present(port); +} + +int board_vbus_source_enabled(int port) +{ + return ppc_is_sourcing_vbus(port); +} + +/* ----------------- Vendor Defined Messages ------------------ */ +const struct svdm_response svdm_rsp = { + .identity = NULL, + .svids = NULL, + .modes = NULL, +}; + +int pd_custom_vdm(int port, int cnt, uint32_t *payload, + uint32_t **rpayload) +{ + int cmd = PD_VDO_CMD(payload[0]); + uint16_t dev_id = 0; + int is_rw, is_latest; + + /* make sure we have some payload */ + if (cnt == 0) + return 0; + + switch (cmd) { + case VDO_CMD_VERSION: + /* guarantee last byte of payload is null character */ + *(payload + cnt - 1) = 0; + CPRINTF("version: %s\n", (char *)(payload+1)); + break; + case VDO_CMD_READ_INFO: + case VDO_CMD_SEND_INFO: + /* copy hash */ + if (cnt == 7) { + dev_id = VDO_INFO_HW_DEV_ID(payload[6]); + is_rw = VDO_INFO_IS_RW(payload[6]); + + is_latest = pd_dev_store_rw_hash(port, + dev_id, + payload + 1, + is_rw ? + SYSTEM_IMAGE_RW : + SYSTEM_IMAGE_RO); + /* + * Send update host event unless our RW hash is + * already known to be the latest update RW. + */ + if (!is_rw || !is_latest) + pd_send_host_event(PD_EVENT_UPDATE_DEVICE); + + CPRINTF("DevId:%d.%d SW:%d RW:%d\n", + HW_DEV_ID_MAJ(dev_id), + HW_DEV_ID_MIN(dev_id), + VDO_INFO_SW_DBG_VER(payload[6]), + is_rw); + } else if (cnt == 6) { + /* really old devices don't have last byte */ + pd_dev_store_rw_hash(port, dev_id, payload + 1, + SYSTEM_IMAGE_UNKNOWN); + } + break; + case VDO_CMD_CURRENT: + CPRINTF("Current: %dmA\n", payload[1]); + break; + case VDO_CMD_FLIP: + usb_mux_flip(port); + break; +#ifdef CONFIG_USB_PD_LOGGING + case VDO_CMD_GET_LOG: + pd_log_recv_vdm(port, cnt, payload); + break; +#endif /* CONFIG_USB_PD_LOGGING */ + } + + return 0; +} + +#ifdef CONFIG_USB_PD_ALT_MODE_DFP +static int dp_flags[CONFIG_USB_PD_PORT_COUNT]; +static uint32_t dp_status[CONFIG_USB_PD_PORT_COUNT]; + +static int svdm_enter_dp_mode(int port, uint32_t mode_caps) +{ + dp_flags[port] = 0; + dp_status[port] = 0; + + /* Only enter mode if device is DFP_D capable */ + if (mode_caps & MODE_DP_SNK) + return 0; + + return -1; +} + +static int svdm_dp_status(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_STATUS | VDO_OPOS(opos)); + payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */ + 0, /* HPD level ... not applicable */ + 0, /* exit DP? ... no */ + 0, /* usb mode? ... no */ + 0, /* multi-function ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON)), + 0, /* power low? ... no */ + (!!(dp_flags[port] & DP_FLAGS_DP_ON))); + return 2; +}; + +static enum typec_mux svdm_dp_mux_mode(int port) +{ + int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); + int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); + /* + * Multi-function operation is only allowed if that pin config is + * supported. + */ + if ((pin_mode & MODE_DP_PIN_MF_MASK) && mf_pref) + return TYPEC_MUX_DOCK; + else + return TYPEC_MUX_DP; +} + +static int svdm_dp_config(int port, uint32_t *payload) +{ + int opos = pd_alt_mode(port, USB_SID_DISPLAYPORT); + int mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); + int pin_mode = pd_dfp_dp_get_pin_mode(port, dp_status[port]); + enum typec_mux mux_mode = svdm_dp_mux_mode(port); + + if (!pin_mode) + return 0; + + CPRINTS("pin_mode: %x, mf: %d, mux: %d", pin_mode, mf_pref, mux_mode); + + /* + * Place the USB Type-C pins that are to be re-configured to DisplayPort + * Configuration into the Safe state. For TYPEC_MUX_DOCK, the superspeed + * signals can remain connected. For TYPEC_MUX_DP, disconnect the + * superspeed signals here, before the pins are re-configured to + * DisplayPort (in svdm_dp_post_config, when we receive the config ack). + */ + if (mux_mode == TYPEC_MUX_DP) + usb_mux_set(port, TYPEC_MUX_NONE, USB_SWITCH_CONNECT, + pd_get_polarity(port)); + + payload[0] = VDO(USB_SID_DISPLAYPORT, 1, + CMD_DP_CONFIG | VDO_OPOS(opos)); + payload[1] = VDO_DP_CFG(pin_mode, /* pin mode */ + 1, /* DPv1.3 signaling */ + 2); /* UFP connected */ + return 2; +}; + +/* + * timestamp of the next possible toggle to ensure the 2-ms spacing + * between IRQ_HPD. + */ +static uint64_t hpd_deadline[CONFIG_USB_PD_PORT_COUNT]; + +#define PORT_TO_HPD(port) ((port) ? GPIO_USB_C1_DP_HPD : GPIO_USB_C0_DP_HPD) +static void svdm_dp_post_config(int port) +{ + const struct usb_mux * const mux = &usb_muxes[port]; + + /* Connect the SBU and USB lines to the connector. */ + ppc_set_sbu(port, 1); + usb_mux_set(port, svdm_dp_mux_mode(port), USB_SWITCH_CONNECT, + pd_get_polarity(port)); + + dp_flags[port] |= DP_FLAGS_DP_ON; + if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) + return; + + gpio_set_level(PORT_TO_HPD(port), 1); + + /* set the minimum time delay (2ms) for the next HPD IRQ */ + hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + mux->hpd_update(port, 1, 0); +} + +static int svdm_dp_attention(int port, uint32_t *payload) +{ + int cur_lvl; + int lvl = PD_VDO_DPSTS_HPD_LVL(payload[1]); + int irq = PD_VDO_DPSTS_HPD_IRQ(payload[1]); + enum gpio_signal hpd = PORT_TO_HPD(port); + const struct usb_mux * const mux = &usb_muxes[port]; + + cur_lvl = gpio_get_level(hpd); + dp_status[port] = payload[1]; + + /* Its initial DP status message prior to config */ + if (!(dp_flags[port] & DP_FLAGS_DP_ON)) { + if (lvl) + dp_flags[port] |= DP_FLAGS_HPD_HI_PENDING; + return 1; /* ack */ + } + + if (irq && cur_lvl) { + uint64_t now = get_time().val; + /* wait for the minimum spacing between IRQ_HPD if needed */ + if (now < hpd_deadline[port]) + usleep(hpd_deadline[port] - now); + + /* generate IRQ_HPD pulse */ + gpio_set_level(hpd, 0); + usleep(HPD_DSTREAM_DEBOUNCE_IRQ); + gpio_set_level(hpd, 1); + + /* set the minimum time delay (2ms) for the next HPD IRQ */ + hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + } else if (irq && !lvl) { + /* + * IRQ can only be generated when the level is high, because + * the IRQ is signaled by a short low pulse from the high level. + */ + CPRINTF("ERR:HPD:IRQ&LOW\n"); + return 0; /* nak */ + } else { + gpio_set_level(hpd, lvl); + /* set the minimum time delay (2ms) for the next HPD IRQ */ + hpd_deadline[port] = get_time().val + HPD_USTREAM_DEBOUNCE_LVL; + } + mux->hpd_update(port, lvl, irq); + return 1; /* ack */ +} + +static void svdm_exit_dp_mode(int port) +{ + const struct usb_mux * const mux = &usb_muxes[port]; + + dp_flags[port] = 0; + dp_status[port] = 0; + + usb_mux_set(port, TYPEC_MUX_NONE, USB_SWITCH_CONNECT, + pd_get_polarity(port)); + gpio_set_level(PORT_TO_HPD(port), 0); + mux->hpd_update(port, 0, 0); +} + +static int svdm_enter_gfu_mode(int port, uint32_t mode_caps) +{ + /* Always enter GFU mode */ + return 0; +} + +static void svdm_exit_gfu_mode(int port) +{ +} + +static int svdm_gfu_status(int port, uint32_t *payload) +{ + /* + * This is called after enter mode is successful, send unstructured + * VDM to read info. + */ + pd_send_vdm(port, USB_VID_GOOGLE, VDO_CMD_READ_INFO, NULL, 0); + return 0; +} + +static int svdm_gfu_config(int port, uint32_t *payload) +{ + return 0; +} + +static int svdm_gfu_attention(int port, uint32_t *payload) +{ + return 0; +} + +const struct svdm_amode_fx supported_modes[] = { + { + .svid = USB_SID_DISPLAYPORT, + .enter = &svdm_enter_dp_mode, + .status = &svdm_dp_status, + .config = &svdm_dp_config, + .post_config = &svdm_dp_post_config, + .attention = &svdm_dp_attention, + .exit = &svdm_exit_dp_mode, + }, + { + .svid = USB_VID_GOOGLE, + .enter = &svdm_enter_gfu_mode, + .status = &svdm_gfu_status, + .config = &svdm_gfu_config, + .attention = &svdm_gfu_attention, + .exit = &svdm_exit_gfu_mode, + } +}; +const int supported_modes_cnt = ARRAY_SIZE(supported_modes); +#endif /* CONFIG_USB_PD_ALT_MODE_DFP */ diff --git a/board/trembyle/analyzestack.yaml b/board/trembyle/analyzestack.yaml new file mode 120000 index 0000000000..4c09084128 --- /dev/null +++ b/board/trembyle/analyzestack.yaml @@ -0,0 +1 @@ +../../baseboard/zork/analyzestack.yaml \ No newline at end of file diff --git a/board/trembyle/battery.c b/board/trembyle/battery.c new file mode 100644 index 0000000000..13e3f71a6c --- /dev/null +++ b/board/trembyle/battery.c @@ -0,0 +1,65 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Battery pack vendor provided charging profile + */ + +#include "battery_fuel_gauge.h" +#include "common.h" +#include "util.h" + +/* + * Battery info for all Zork battery types. Note that the fields + * start_charging_min/max and charging_min/max are not used for the charger. + * The effective temperature limits are given by discharging_min/max_c. + * + * Fuel Gauge (FG) parameters which are used for determining if the battery + * is connected, the appropriate ship mode (battery cutoff) command, and the + * charge/discharge FETs status. + * + * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery + * register. For some batteries, the charge/discharge FET bits are set when + * charging/discharging is active, in other types, these bits set mean that + * charging/discharging is disabled. Therefore, in addition to the mask for + * these bits, a disconnect value must be specified. Note that for TI fuel + * gauge, the charge/discharge FET status is found in Operation Status (0x54), + * but a read of Manufacturer Access (0x00) will return the lower 16 bits of + * Operation status which contains the FET status bits. + * + * The assumption for battery types supported is that the charge/discharge FET + * status can be read with a sb_read() command and therefore, only the register + * address, mask, and disconnect value need to be provided. + */ +const struct board_batt_params board_battery_info[] = { + /* Panasonic AP15O5L Battery Information */ + [BATTERY_PANASONIC] = { + .fuel_gauge = { + .manuf_name = "PANASONIC", + .ship_mode = { + .reg_addr = 0x3A, + .reg_data = { 0xC574, 0xC574 }, + }, + .fet = { + .reg_addr = 0x0, + .reg_mask = 0x4000, + .disconnect_val = 0x0, + } + }, + .batt_info = { + .voltage_max = 13200, + .voltage_normal = 11550, /* mV */ + .voltage_min = 9000, /* mV */ + .precharge_current = 256, /* mA */ + .start_charging_min_c = 0, + .start_charging_max_c = 50, + .charging_min_c = 0, + .charging_max_c = 60, + .discharging_min_c = 0, + .discharging_max_c = 60, + }, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT); + +const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_PANASONIC; diff --git a/board/trembyle/board.c b/board/trembyle/board.c new file mode 100644 index 0000000000..879fc2d945 --- /dev/null +++ b/board/trembyle/board.c @@ -0,0 +1,249 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zork board-specific configuration */ + +#include "adc.h" +#include "adc_chip.h" +#include "button.h" +#include "charge_manager.h" +#include "charge_state.h" +#include "charge_state_v2.h" +#include "common.h" +#include "compile_time_macros.h" +#include "console.h" +#include "driver/accel_kionix.h" +#include "driver/accel_kx022.h" +#include "driver/accelgyro_bmi160.h" +#include "driver/led/lm3630a.h" +#include "driver/ppc/sn5s330.h" +#include "driver/tcpm/anx74xx.h" +#include "driver/tcpm/ps8xxx.h" +#include "driver/temp_sensor/sb_tsi.h" +#include "ec_commands.h" +#include "extpower.h" +#include "gpio.h" +#include "hooks.h" +#include "i2c.h" +#include "keyboard_scan.h" +#include "lid_switch.h" +#include "motion_sense.h" +#include "power.h" +#include "power_button.h" +#include "pwm.h" +#include "pwm_chip.h" +#include "registers.h" +#include "switch.h" +#include "system.h" +#include "task.h" +#include "tcpci.h" +#include "temp_sensor.h" +#include "thermistor.h" +#include "usb_mux.h" +#include "usb_pd_tcpm.h" +#include "usbc_ppc.h" +#include "util.h" + +#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args) + +#ifdef CONFIG_USB_PD_TCPC_LOW_POWER +static void anx74xx_cable_det_handler(void) +{ + int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET); + int reset_n = gpio_get_level(GPIO_USB_C0_PD_RST_L); + + /* + * A cable_det low->high transition was detected. If following the + * debounce time, cable_det is high, and reset_n is low, then ANX3429 is + * currently in standby mode and needs to be woken up. Set the + * TCPC_RESET event which will bring the ANX3429 out of standby + * mode. Setting this event is gated on reset_n being low because the + * ANX3429 will always set cable_det when transitioning to normal mode + * and if in normal mode, then there is no need to trigger a tcpc reset. + */ + if (cable_det && !reset_n) + task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0); +} +DECLARE_DEFERRED(anx74xx_cable_det_handler); + +void anx74xx_cable_det_interrupt(enum gpio_signal signal) +{ + /* debounce for 2 msec */ + hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC)); +} +#endif + +static void ppc_interrupt(enum gpio_signal signal) +{ + int port = (signal == GPIO_USB_C0_SWCTL_INT_ODL) ? 0 : 1; + + sn5s330_interrupt(port); +} + +#include "gpio_list.h" + +/* I2C port map. */ +const struct i2c_port_t i2c_ports[] = { + {"power", I2C_PORT_POWER, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA}, + {"tcpc0", I2C_PORT_TCPC0, 400, GPIO_I2C1_SCL, GPIO_I2C1_SDA}, + {"tcpc1", I2C_PORT_TCPC1, 400, GPIO_I2C2_SCL, GPIO_I2C2_SDA}, + {"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA}, + {"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}, + {"sensor", I2C_PORT_SENSOR, 400, GPIO_I2C7_SCL, GPIO_I2C7_SDA}, +}; +const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); + +/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */ +const struct pwm_t pwm_channels[] = { + [PWM_CH_KBLIGHT] = { + .channel = 5, + .flags = PWM_CONFIG_DSLEEP, + .freq = 100, + }, + [PWM_CH_LED1_AMBER] = { + .channel = 0, + .flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW + | PWM_CONFIG_DSLEEP), + .freq = 100, + }, + [PWM_CH_LED2_BLUE] = { + .channel = 2, + .flags = (PWM_CONFIG_OPEN_DRAIN | PWM_CONFIG_ACTIVE_LOW + | PWM_CONFIG_DSLEEP), + .freq = 100, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); + +void board_update_sensor_config_from_sku(void) +{ + /* Enable Gyro interrupts */ + gpio_enable_interrupt(GPIO_6AXIS_INT_L); +} + +void board_overcurrent_event(int port, int is_overcurrented) +{ + enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L + : GPIO_USB_C1_OC_L; + /* Note that the levels are inverted because the pin is active low. */ + int lvl = is_overcurrented ? 0 : 1; + + gpio_set_level(signal, lvl); + + CPRINTS("p%d: overcurrent!", port); +} + +void board_tcpc_init(void) +{ + int port; + + /* Only reset TCPC if not sysjump */ + if (!system_jumped_to_this_image()) + board_reset_pd_mcu(); + + /* Enable PPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL); + + /* Enable TCPC interrupts. */ + gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL); + +#ifdef CONFIG_USB_PD_TCPC_LOW_POWER + /* Enable CABLE_DET interrupt for ANX3429 wake from standby */ + gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET); +#endif + /* + * Initialize HPD to low; after sysjump SOC needs to see + * HPD pulse to enable video path + */ + for (port = 0; port < CONFIG_USB_PD_PORT_COUNT; port++) { + const struct usb_mux *mux = &usb_muxes[port]; + + mux->hpd_update(port, 0, 0); + } +} +DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1); + +uint16_t tcpc_get_alert_status(void) +{ + uint16_t status = 0; + + if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) { + if (gpio_get_level(GPIO_USB_C0_PD_RST_L)) + status |= PD_STATUS_TCPC_ALERT_0; + } + + if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) { + if (gpio_get_level(GPIO_USB_C1_PD_RST_L)) + status |= PD_STATUS_TCPC_ALERT_1; + } + + return status; +} + +/** + * Power on (or off) a single TCPC. + * minimum on/off delays are included. + * + * @param port Port number of TCPC. + * @param mode 0: power off, 1: power on. + */ +void board_set_tcpc_power_mode(int port, int mode) +{ + if (port != USB_PD_PORT_ANX74XX) + return; + + switch (mode) { + case ANX74XX_NORMAL_MODE: + gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1); + msleep(ANX74XX_PWR_H_RST_H_DELAY_MS); + gpio_set_level(GPIO_USB_C0_PD_RST_L, 1); + break; + case ANX74XX_STANDBY_MODE: + gpio_set_level(GPIO_USB_C0_PD_RST_L, 0); + msleep(ANX74XX_RST_L_PWR_L_DELAY_MS); + gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0); + msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS); + break; + default: + break; + } +} + +void board_reset_pd_mcu(void) +{ + /* Assert reset to TCPC1 (ps8751) */ + gpio_set_level(GPIO_USB_C1_PD_RST_L, 0); + + /* Assert reset to TCPC0 (anx3429) */ + gpio_set_level(GPIO_USB_C0_PD_RST_L, 0); + + /* TCPC1 (ps8751) requires 1ms reset down assertion */ + msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS)); + + /* Deassert reset to TCPC1 */ + gpio_set_level(GPIO_USB_C1_PD_RST_L, 1); + /* Disable TCPC0 power */ + gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0); + + /* + * anx3429 requires 10ms reset/power down assertion + */ + msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS); + board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1); +} + +static void board_kblight_init(void) +{ + /* + * Enable keyboard backlight. This needs to be done here because + * the chip doesn't have power until PP3300_S0 comes up. + */ + gpio_set_level(GPIO_KB_BL_EN, 1); + lm3630a_poweron(); +} +DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT); diff --git a/board/trembyle/board.h b/board/trembyle/board.h new file mode 100644 index 0000000000..c7b71e6dd9 --- /dev/null +++ b/board/trembyle/board.h @@ -0,0 +1,83 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Zork board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +#include "baseboard.h" + +/* + * By default, enable all console messages excepted HC, ACPI and event: + * The sensor stack is generating a lot of activity. + */ +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#undef CONFIG_HOSTCMD_DEBUG_MODE +#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF + +#define CONFIG_MKBP_USE_HOST_EVENT + +/* Work around Zork KSI03 HW bug and rework (b/79758966) */ +#define CONFIG_KEYBOARD_REFRESH_ROW3 +#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI3 + +/* Power and battery LEDs */ +#define CONFIG_LED_COMMON +#define CONFIG_CMD_LEDTEST + +#undef CONFIG_LED_PWM_NEAR_FULL_COLOR +#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR +#undef CONFIG_LED_PWM_SOC_ON_COLOR +#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR + +#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_BLUE +#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER +#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE +#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_BLUE + +#define CONFIG_LED_PWM_COUNT 1 + +#define I2C_PORT_KBLIGHT NPCX_I2C_PORT5_0 + +/* KB backlight driver */ +#define CONFIG_LED_DRIVER_LM3630A + +/* Motion sensing drivers */ +#define CONFIG_ACCELGYRO_BMI160 +#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \ + TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL) +#define CONFIG_ACCEL_INTERRUPTS +#define CONFIG_ACCEL_KX022 +#define CONFIG_CMD_ACCELS +#define CONFIG_CMD_ACCEL_INFO +#define CONFIG_TABLET_MODE +#define CONFIG_LID_ANGLE +#define CONFIG_LID_ANGLE_UPDATE +#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL +#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL +/* + * Slew rate on the PP1800_SENSOR load switch requires a short delay on startup. + */ +#undef CONFIG_MOTION_SENSE_RESUME_DELAY_US +#define CONFIG_MOTION_SENSE_RESUME_DELAY_US (10 * MSEC) + +#ifndef __ASSEMBLER__ + +enum pwm_channel { + PWM_CH_KBLIGHT = 0, + PWM_CH_LED1_AMBER, + PWM_CH_LED2_BLUE, + PWM_CH_COUNT +}; + +enum battery_type { + BATTERY_PANASONIC, + BATTERY_TYPE_COUNT, +}; + +#endif /* !__ASSEMBLER__ */ + +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/trembyle/build.mk b/board/trembyle/build.mk new file mode 100644 index 0000000000..7508f379d3 --- /dev/null +++ b/board/trembyle/build.mk @@ -0,0 +1,15 @@ +# -*- makefile -*- +# Copyright 2019 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +CHIP:=npcx +CHIP_FAMILY:=npcx7 +CHIP_VARIANT:=npcx7m6f +BASEBOARD:=zork + +board-y=board.o led.o +board-$(CONFIG_BATTERY_SMART)+=battery.o diff --git a/board/trembyle/ec.tasklist b/board/trembyle/ec.tasklist new file mode 100644 index 0000000000..4c4a4898b1 --- /dev/null +++ b/board/trembyle/ec.tasklist @@ -0,0 +1,26 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* + * See CONFIG_TASK_LIST in config.h for details. + */ + +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \ + TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \ + TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \ + TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE) diff --git a/board/trembyle/gpio.inc b/board/trembyle/gpio.inc new file mode 100644 index 0000000000..a6aaee7b4e --- /dev/null +++ b/board/trembyle/gpio.inc @@ -0,0 +1,115 @@ +/* -*- mode:c -*- + * + * Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +GPIO_INT(USB_C0_PD_INT_ODL, PIN(A, 0), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C1_PD_INT_ODL, PIN(F, 5), GPIO_INT_FALLING, tcpc_alert_event) +GPIO_INT(USB_C0_SWCTL_INT_ODL, PIN(0, 3), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(USB_C1_SWCTL_INT_ODL, PIN(D, 4), GPIO_INT_FALLING, ppc_interrupt) +GPIO_INT(PCH_SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(PCH_SLP_S5_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(S0_PGOOD, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(S5_PGOOD, PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) +GPIO_INT(POWER_BUTTON_L, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH | GPIO_PULL_UP, lid_interrupt) +GPIO_INT(AC_PRESENT, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) +GPIO_INT(WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) +GPIO_INT(VOLUME_DOWN_L, PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(VOLUME_UP_L, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) +GPIO_INT(USB_C0_CABLE_DET, PIN(3, 7), GPIO_INT_RISING, anx74xx_cable_det_interrupt) +GPIO_INT(6AXIS_INT_L, PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt) + +GPIO(EN_PWR_A, PIN(E, 2), GPIO_OUT_LOW) /* Enable Power */ +GPIO(EN_PP1800_SENSOR, PIN(6, 7), GPIO_OUT_LOW) /* Enable Power */ +GPIO(ENABLE_BACKLIGHT_L, PIN(D, 3), GPIO_OUT_HIGH) /* Enable Backlight */ +GPIO(PCH_RSMRST_L, PIN(C, 2), GPIO_OUT_LOW) /* RSMRST# to SOC */ +GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_OUT_HIGH) /* Power Button to SOC */ +GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_OUT_HIGH) /* Wake SOC */ +GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* Cold Reset to SOC */ +GPIO(CCD_MODE_ODL, PIN(E, 3), GPIO_INPUT) /* Case Closed Debug Mode */ +GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW) /* EC Entering RW */ +GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP) /* Battery Present */ +GPIO(PCH_SYS_PWROK, PIN(D, 6), GPIO_OUT_LOW) /* Power OK to SOC */ +GPIO(EC_APU_RST, PIN(E, 4), GPIO_INPUT) /* Reset to SOC */ +GPIO(CPU_PROCHOT, PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V) /* PROCHOT to SOC */ +GPIO(APU_ALERT_L, PIN(A, 2), GPIO_INPUT) /* Alert to SOC */ +GPIO(3AXIS_INT_L, PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* 3 Axis Accel */ +GPIO(KB_BL_EN, PIN(F, 2), GPIO_OUT_LOW) /* Enable KB Backlight */ + +/* I2C pins - these will be reconfigured for alternate function below */ +GPIO(I2C0_SCL, PIN(B, 5), GPIO_INPUT) /* EC_I2C_POWER_SCL */ +GPIO(I2C0_SDA, PIN(B, 4), GPIO_INPUT) /* EC_I2C_POWER_SDA */ +GPIO(I2C1_SCL, PIN(9, 0), GPIO_INPUT) /* EC_I2C_USB_C0_PD_SCL */ +GPIO(I2C1_SDA, PIN(8, 7), GPIO_INPUT) /* EC_I2C_USB_C0_PD_SDA */ +GPIO(I2C2_SCL, PIN(9, 2), GPIO_INPUT) /* EC_I2C_USB_C1_PD_SCL */ +GPIO(I2C2_SDA, PIN(9, 1), GPIO_INPUT) /* EC_I2C_USB_C1_PD_SDA */ +GPIO(I2C3_SCL, PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V) /* APU_SIC */ +GPIO(I2C3_SDA, PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V) /* APU_SID */ +GPIO(I2C5_SCL, PIN(3, 3), GPIO_INPUT) /* EC_I2C_EEPROM_SCL and + EC_I2C_KB_BL_SCL */ +GPIO(I2C5_SDA, PIN(3, 6), GPIO_INPUT) /* EC_I2C_EEPROM_SDA and + EC_I2C_KB_BL_SDA */ +GPIO(I2C7_SCL, PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_SENSOR_SCL */ +GPIO(I2C7_SDA, PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V) /* EC_I2C_SENSOR_SDA */ + +/* + * The NPCX LPC driver configures and controls SCI and SMI, + * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are + * not defined here as GPIOs. + */ +GPIO(PCH_SLP_S0_L, PIN(A, 4), GPIO_INPUT) + +GPIO(EN_USB_A0_5V, PIN(6, 1), GPIO_OUT_LOW) /* Enable A0 5V Charging */ +GPIO(EN_USB_A1_5V, PIN(C, 0), GPIO_OUT_LOW) /* Enable A1 5V Charging */ +GPIO(EN_USB_C0_TCPC_PWR, PIN(6, 0), GPIO_OUT_LOW) /* Enable C0 TCPC Power */ +GPIO(USB_C0_OC_L, PIN(7, 3), GPIO_OUT_HIGH) /* C0 Over Current */ +GPIO(USB_C1_OC_L, PIN(7, 2), GPIO_OUT_HIGH) /* C1 Over Current */ +GPIO(USB_C0_PD_RST_L, PIN(3, 2), GPIO_OUT_HIGH) /* C0 PD Reset */ +GPIO(USB_C1_PD_RST_L, PIN(D, 5), GPIO_OUT_HIGH) /* C1 PD Reset */ +GPIO(USB_C0_BC12_VBUS_ON_L, PIN(4, 0), GPIO_ODR_HIGH) /* C0 BC1.2 Power */ +GPIO(USB_C1_BC12_VBUS_ON_L, PIN(B, 1), GPIO_ODR_HIGH | GPIO_PULL_UP) /* C1 BC1.2 Power */ +GPIO(USB_C0_BC12_CHG_DET, PIN(6, 2), GPIO_INPUT) /* C0 BC1.2 Detect */ +GPIO(USB_C1_BC12_CHG_DET, PIN(8, 3), GPIO_INPUT | GPIO_PULL_DOWN) /* C1 BC1.2 Detect */ +GPIO(USB_C0_DP_HPD, PIN(9, 5), GPIO_OUT_LOW) /* C0 DP Hotplug Detect */ +GPIO(USB_C1_DP_HPD, PIN(9, 6), GPIO_OUT_LOW) /* C1 DP Hotplug Detect */ + +/* Board ID */ +GPIO(BOARD_VERSION1, PIN(C, 7), GPIO_INPUT) +GPIO(BOARD_VERSION2, PIN(9, 3), GPIO_INPUT) +GPIO(BOARD_VERSION3, PIN(8, 0), GPIO_INPUT) +GPIO(SKU_ID1, PIN(F, 0), GPIO_INPUT) +GPIO(SKU_ID2, PIN(4, 1), GPIO_INPUT) + +/* Alternate functions GPIO definitions */ +/* Cr50 requires no pull-ups on UART pins. */ +ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0) /* UART from EC to Servo */ +ALTERNATE(PIN_MASK(B, 0x30), 0, MODULE_I2C, 0) /* I2C0 */ +ALTERNATE(PIN_MASK(9, 0x07), 0, MODULE_I2C, 0) /* I2C1 SCL / I2C2 */ +ALTERNATE(PIN_MASK(8, 0x80), 0, MODULE_I2C, 0) /* I2C1 SDA */ +ALTERNATE(PIN_MASK(D, 0x03), 0, MODULE_I2C, 0) /* I2C3 */ +ALTERNATE(PIN_MASK(3, 0x48), 0, MODULE_I2C, 0) /* I2C5 */ +ALTERNATE(PIN_MASK(B, 0x0C), 0, MODULE_I2C, 0) /* I2C7 */ +ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ +ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0) /* ADC4 */ +ALTERNATE(PIN_MASK(F, 0x02), 0, MODULE_ADC, 0) /* ADC8 */ +ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0) /* ADC9 */ +ALTERNATE(PIN_MASK(B, 0x80), 0, MODULE_PWM, 0) /* KB Backlight */ +ALTERNATE(PIN_MASK(C, 0x18), 0, MODULE_PWM, 0) /* LED 1 & 2 */ + +/* Keyboard Pins */ +ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_00-01 */ +ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT) /* KSI_02-07 */ +ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_00-01 */ +GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW) /* KSO_02 inverted */ +ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_03-09 */ +ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) /* KSO_10-12 */ + +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(0, 0x03), 0, MODULE_PMU, 0) /* GPIO00, GPIO01 */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 */ diff --git a/board/trembyle/led.c b/board/trembyle/led.c new file mode 100644 index 0000000000..8d783c6a87 --- /dev/null +++ b/board/trembyle/led.c @@ -0,0 +1,66 @@ +/* Copyright 2019 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "ec_commands.h" +#include "led_pwm.h" +#include "util.h" + +const enum ec_led_id supported_led_ids[] = { + EC_LED_ID_POWER_LED, +}; +const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids); + +/* + * We only have a blue and an amber LED, so setting any other colour results in + * both LEDs being off. + */ +struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = { + /* Amber, Blue */ + [EC_LED_COLOR_RED] = { 0, 0 }, + [EC_LED_COLOR_GREEN] = { 0, 0 }, + [EC_LED_COLOR_BLUE] = { 0, 100 }, + [EC_LED_COLOR_YELLOW] = { 0, 0 }, + [EC_LED_COLOR_WHITE] = { 0, 0 }, + [EC_LED_COLOR_AMBER] = { 100, 0 }, +}; + +/* One logical LED with amber and blue channels. */ +struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = { + { + PWM_CH_LED1_AMBER, + PWM_CH_LED2_BLUE, + PWM_LED_NO_CHANNEL, + }, +}; + +void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range) +{ + memset(brightness_range, '\0', + sizeof(*brightness_range) * EC_LED_COLOR_COUNT); + brightness_range[EC_LED_COLOR_AMBER] = 100; + brightness_range[EC_LED_COLOR_BLUE] = 100; +} + +int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness) +{ + enum pwm_led_id pwm_id; + + /* Convert ec_led_id to pwm_led_id. */ + if (led_id == EC_LED_ID_POWER_LED) + pwm_id = PWM_LED0; + else + return EC_ERROR_UNKNOWN; + + if (brightness[EC_LED_COLOR_BLUE]) + set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE); + else if (brightness[EC_LED_COLOR_AMBER]) + set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER); + else + /* Otherwise, the "color" is "off". */ + set_pwm_led_color(pwm_id, -1); + + return EC_SUCCESS; +} -- cgit v1.2.1