From fba4f335a9a78f4112980fcf1cc36d44cfda0406 Mon Sep 17 00:00:00 2001 From: Anton Staaf Date: Mon, 10 Aug 2015 14:49:34 -0700 Subject: cortex-m0: Constrain target register in atomic read One more register constaint needed to be added to the cortex-m0 atomic inline assembly. Vincent fixed all the others. The requirement for ARMv6-m includes that the target load register be one of the low registers as well. Signed-off-by: Anton Staaf BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e Reviewed-on: https://chromium-review.googlesource.com/292435 Trybot-Ready: Anton Staaf Tested-by: Anton Staaf Reviewed-by: Vincent Palatin Commit-Queue: Anton Staaf --- core/cortex-m0/atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 32260ada07..e2df0f2a93 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -56,7 +56,7 @@ static inline uint32_t atomic_read_clear(uint32_t volatile *addr) " ldr %0, [%1]\n" " str %2, [%1]\n" " cpsie i\n" - : "=&r" (ret) + : "=&b" (ret) : "b" (addr), "r" (0) : "cc"); return ret; -- cgit v1.2.1