From 08883e9b4175b726e037d9814497abd65f6dc894 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 13:15:58 -0600 Subject: baseboard/intelrvp/baseboard.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I1d5e4f914425999573167b430787347b4184ab8d Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727895 Reviewed-by: Jeremy Bettis --- baseboard/intelrvp/baseboard.h | 45 ++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 24 deletions(-) (limited to 'baseboard/intelrvp/baseboard.h') diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 9b497568e7..035d7150ec 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -12,13 +12,13 @@ #include "stdbool.h" #ifdef VARIANT_INTELRVP_EC_IT8320 - #include "ite_ec.h" +#include "ite_ec.h" #elif defined(VARIANT_INTELRVP_EC_MCHP) - #include "mchp_ec.h" +#include "mchp_ec.h" #elif defined(VARIANT_INTELRVP_EC_NPCX) - #include "npcx_ec.h" +#include "npcx_ec.h" #else - #error "Define EC chip variant" +#error "Define EC chip variant" #endif /* @@ -27,7 +27,7 @@ */ #define CONFIG_SYSTEM_UNLOCKED -#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) +#define CC_DEFAULT (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC))) #undef CONFIG_HOSTCMD_DEBUG_MODE /* @@ -51,7 +51,7 @@ #define CONFIG_MAX695X_SEVEN_SEGMENT_DISPLAY /* RVP ID read retry count */ -#define RVP_VERSION_READ_RETRY_CNT 2 +#define RVP_VERSION_READ_RETRY_CNT 2 /* Battery */ #define CONFIG_BATTERY_CUT_OFF @@ -66,7 +66,7 @@ #define CONFIG_CHARGER_INPUT_CURRENT 512 #define CONFIG_CHARGER_SENSE_RESISTOR 5 #define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 -#undef CONFIG_EXTPOWER_DEBOUNCE_MS +#undef CONFIG_EXTPOWER_DEBOUNCE_MS #define CONFIG_EXTPOWER_DEBOUNCE_MS 200 #define CONFIG_EXTPOWER_GPIO #define CONFIG_TRICKLE_CHARGING @@ -75,8 +75,8 @@ * Don't allow the system to boot to S0 when the battery is low and unable to * communicate on locked systems (which haven't PD negotiated) */ -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 -#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT 15000 +#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 15001 /* Keyboard */ @@ -109,7 +109,7 @@ /* USB MUX */ #ifdef CONFIG_USB_MUX_VIRTUAL - #define CONFIG_HOSTCMD_LOCATE_CHIP +#define CONFIG_HOSTCMD_LOCATE_CHIP #endif #define CONFIG_USBC_SS_MUX @@ -152,13 +152,13 @@ /* Temperature sensor */ #ifdef CONFIG_TEMP_SENSOR - #define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B - #define CONFIG_TEMP_SENSOR_POWER - #define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A - #define CONFIG_THERMISTOR - #define CONFIG_THROTTLE_AP +#define CONFIG_STEINHART_HART_3V0_22K6_47K_4050B +#define CONFIG_TEMP_SENSOR_POWER +#define GPIO_TEMP_SENSOR_POWER GPIO_EN_PP3300_A +#define CONFIG_THERMISTOR +#define CONFIG_THROTTLE_AP #ifdef CONFIG_PECI - #define CONFIG_PECI_COMMON +#define CONFIG_PECI_COMMON #endif /* CONFIG_PECI */ #endif /* CONFIG_TEMP_SENSOR */ @@ -177,10 +177,7 @@ FORWARD_DECLARE_ENUM(tcpc_rp_value); /* PWM channels */ -enum pwm_channel { - PWM_CH_FAN, - PWM_CH_COUNT -}; +enum pwm_channel { PWM_CH_FAN, PWM_CH_COUNT }; /* FAN channels */ enum fan_channel { @@ -211,13 +208,13 @@ enum temp_sensor_id { }; /* TODO(b:132652892): Verify the below numbers. */ -#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ +#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */ #define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */ /* Define typical operating power */ -#define PD_OPERATING_POWER_MW 15000 -#define PD_MAX_VOLTAGE_MV 20000 -#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW/PD_MAX_VOLTAGE_MV) * 1000) +#define PD_OPERATING_POWER_MW 15000 +#define PD_MAX_VOLTAGE_MV 20000 +#define PD_MAX_CURRENT_MA ((PD_MAX_POWER_MW / PD_MAX_VOLTAGE_MV) * 1000) #define DC_JACK_MAX_VOLTAGE_MV 19000 /* TCPC gpios */ -- cgit v1.2.1 From 28ba9af251f448140f2e6cc224b2566052f326e8 Mon Sep 17 00:00:00 2001 From: Tom Hughes Date: Wed, 13 Jul 2022 14:30:00 -0700 Subject: baseboard/intelrvp: Enable LTO We're running low on flash space, so enable LTO. Before LTO: RO: 36 bytes in flash and 34972 bytes in RAM still available RW: 20 bytes in flash and 34972 bytes in RAM still available After LTO: RO: 8684 bytes in flash and 35268 bytes in RAM still available RW: 8604 bytes in flash and 35268 bytes in RAM still available BRANCH=none BUG=b:238433667 TEST=make buildall Signed-off-by: Tom Hughes Change-Id: I229e7532672f3bdc3040d6b428049a80144cc1e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3761356 Reviewed-by: Keith Short --- baseboard/intelrvp/baseboard.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'baseboard/intelrvp/baseboard.h') diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 035d7150ec..b003c5a785 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -21,6 +21,8 @@ #error "Define EC chip variant" #endif +#define CONFIG_LTO + /* * Allow dangerous commands. * TODO: Remove this config before production. -- cgit v1.2.1 From cfe06a93f1ee21ef32fe002ccc5a6c8daed27f02 Mon Sep 17 00:00:00 2001 From: Usha P Date: Tue, 26 Jul 2022 09:36:53 +0530 Subject: baseboard/intelrvp: Update LTO configuration This change includes the following, 1. Reverts commit 28ba9af251f448140f2e6cc224b2566052f326e8 Reason for revert : With LTO enabled, WDT (watchdog timer) timeout is observed on ADL-N RVP board followed by boot failure. Flash memory is still available on ADL_N RVP with LTO disabled. *** 57112 bytes in flash and 21592 bytes in RAM still available on adlrvpm_ite RO **** *** 59348 bytes in flash and 21592 bytes in RAM still available on adlrvpm_ite RW **** 2. Enable LTO config only for required board adlrvpp_mchp1521. There is no flash memory left without LTO config enabled for this board. BUG=None BRANCH=main TEST=build and boot ADL-N RVP to OS without any timeout issues. Change-Id: Ic39da119e0cb5f5abeedfc5cb35ded31f235380d Signed-off-by: Usha P Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3787359 Tested-by: Usha P Reviewed-by: Boris Mittelberg Reviewed-by: caveh jalali Reviewed-by: Vijay P Hiremath --- baseboard/intelrvp/baseboard.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'baseboard/intelrvp/baseboard.h') diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index b003c5a785..b374d24b3a 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -21,7 +21,10 @@ #error "Define EC chip variant" #endif -#define CONFIG_LTO +/* + * TODO: b/241322365 - Watchdog error are observed if LTO is enabled + * hence disabled it. Enable LTO once the fix is found. + */ /* * Allow dangerous commands. -- cgit v1.2.1 From 538a24ab36652a61795d108707b891c3ad4867cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Barna=C5=9B?= Date: Wed, 17 Nov 2021 17:49:27 +0100 Subject: config: rename HOSTCMD_ESPI_* to HOST_INTERFACE_ESPI_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename ESPI additional configs to match the name of base config that selects ESPI as HOST_INTERFACE. BUG=b:195416058 BRANCH=main TEST=zmake testall && make buildall Change-Id: I137449a1a58b1ea0d9794ebc0900e1b68413819d Signed-off-by: Michał Barnaś Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3291744 Reviewed-by: Sam Hurst Code-Coverage: Zoss --- baseboard/intelrvp/baseboard.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'baseboard/intelrvp/baseboard.h') diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index b374d24b3a..85141c0953 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -121,9 +121,9 @@ /* SoC / PCH */ #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_HOST_INTERFACE_ESPI -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -#define CONFIG_HOSTCMD_ESPI_VW_SLP_S5 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S3 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S4 +#define CONFIG_HOST_INTERFACE_ESPI_VW_SLP_S5 #define CONFIG_MKBP_EVENT #define CONFIG_MKBP_USE_HOST_EVENT #define CONFIG_POWER_BUTTON -- cgit v1.2.1 From 71b2ef709dcb14260f5fdaa3ab4ced005a29fb46 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 12 Sep 2022 14:54:36 -0400 Subject: Update license boilerplate text in source code files Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis Reviewed-by: Jack Rosenthal --- baseboard/intelrvp/baseboard.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'baseboard/intelrvp/baseboard.h') diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h index 85141c0953..b927632fc5 100644 --- a/baseboard/intelrvp/baseboard.h +++ b/baseboard/intelrvp/baseboard.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -- cgit v1.2.1