From 0db750791d92985a30abf46249db308d29eb4d61 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Fri, 30 Jul 2021 17:06:37 +0800 Subject: chip/mt_scp: enable mt8195 cache on shared DRAM BRANCH=none BUG=b:184793035 BUG=b:196756955 TEST=make BOARD=cherry_scp Change-Id: I3b026ae0a14b9317cbfff1aa5838e5c3c7811420 Signed-off-by: Tinghan Shen Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3062704 Reviewed-by: Tzung-Bi Shih Commit-Queue: Tzung-Bi Shih --- baseboard/mtscp-rv32i/baseboard.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'baseboard') diff --git a/baseboard/mtscp-rv32i/baseboard.c b/baseboard/mtscp-rv32i/baseboard.c index e5a5cb61f0..a34a08f1fe 100644 --- a/baseboard/mtscp-rv32i/baseboard.c +++ b/baseboard/mtscp-rv32i/baseboard.c @@ -23,7 +23,11 @@ struct mpu_entry mpu_entries[NR_MPU_ENTRIES] = { #endif /* For SCP sys */ {0x70000000, 0x80000000, MPU_ATTR_W | MPU_ATTR_R}, +#ifdef CHIP_VARIANT_MT8195 + {0x10000000, 0x11400000, MPU_ATTR_C | MPU_ATTR_W | MPU_ATTR_R}, +#else {0x10000000, 0x11400000, MPU_ATTR_W | MPU_ATTR_R}, +#endif }; #include "gpio_list.h" -- cgit v1.2.1