From 7866056f7f40592817d544954a8ba2132b834334 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Thu, 9 Nov 2017 17:03:06 -0800 Subject: coral: Change GPIO_USB_C1_PD_RST_ODL to be ODR_HIGH The reset line for the parade TCPC on port 1, has an external 1k pull up resistor. However, the gpio.inc description for this line was set to ODR_LOW which results in a short reset pulse. This can lead to an external charger seeing an unattach event and dropping VBUS. On some Coral systems with certain chargers this results in a continuous reboot loop when no battery is connected. Changing the default state of this line to ODR_HIGH prevents reset from being pulled low until the EC is intializing the TCPC and fixes the continous reboot loop issue when no battery is connected. BUG=b:68226308 BRANCH=coral TEST=Using Robo system tested with the Lenovo Type C charger and verified that the system can boot up without a battery when connected to port 1. Bitland also verified this change in their test setup and found no failures. Change-Id: Ia16fe8cf770dc91da479497d234a2b6f9679b878 Signed-off-by: Scott Collyer Reviewed-on: https://chromium-review.googlesource.com/762066 Commit-Ready: Furquan Shaikh Tested-by: Scott Collyer Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- board/coral/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/coral') diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc index 642e1fb8d4..b9d4e15db0 100644 --- a/board/coral/gpio.inc +++ b/board/coral/gpio.inc @@ -121,7 +121,7 @@ GPIO(USB1_ENABLE, PIN(0, 0), GPIO_OUT_HIGH) GPIO(EN_USB_TCPC_PWR, PIN(C, 3), GPIO_OUT_LOW) GPIO(USB_C0_PD_RST_L, PIN(0, 3), GPIO_OUT_LOW) /* USB_C0_PD_RST_L */ -GPIO(USB_C1_PD_RST_ODL, PIN(7, 4), GPIO_ODR_LOW) +GPIO(USB_C1_PD_RST_ODL, PIN(7, 4), GPIO_ODR_HIGH) /* * Configure as input to enable @ 1.5A, output-low to turn off, or output-high -- cgit v1.2.1