From 858d87cfaae5182b1d6cf008a7e33766612ab000 Mon Sep 17 00:00:00 2001 From: Randall Spangler Date: Tue, 29 May 2012 16:53:05 -0700 Subject: Add basic SPI support to link This adds SPI transaction support, and a debug command to read a few values from the SPI EEPROM. Note that the SPI controller is normally *disabled* with all its I/Os high-Z, so this will not interfere with main processor or Servo on the SPI bus. The bus is only enabled during the SPIROM command itself. BUG=chrome-os-partner:7844 TEST=manual 1) Reboot system 2) on EC console, 'spirom'. Should print Man/Dev ID : 0xef 0x16 JEDEC ID : 0xef 0x40 0x17 Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32 Status reg 1: 0x00 Status reg 2: 0x00 Note that unique ID is, well, unique, so it won't match my value. But it should still be something not all 0xff's. 3) Power on the system. x86 should still boot normally, indicating that the EC isn't interfering with the SPI bus. Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8 --- board/link/board.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board/link/board.c') diff --git a/board/link/board.c b/board/link/board.c index 3ff559c1a9..2a39e76eab 100644 --- a/board/link/board.c +++ b/board/link/board.c @@ -101,6 +101,7 @@ const struct gpio_info gpio_list[GPIO_COUNT] = { {"PCH_SUSACKn", LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL}, {"RADIO_ENABLE_WLAN", LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL}, {"RADIO_ENABLE_BT", LM4_GPIO_D, (1<<1), GPIO_OUT_LOW, NULL}, + {"SPI_CSn", LM4_GPIO_A, (1<<3), GPIO_HI_Z, NULL}, {"TOUCHSCREEN_RESETn", LM4_GPIO_B, (1<<0), GPIO_OUT_LOW, NULL}, {"USB1_CTL1", LM4_GPIO_E, (1<<2), GPIO_OUT_LOW, NULL}, {"USB1_CTL2", LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL}, -- cgit v1.2.1