From 7d9d31e4d9706d4f5cc8859d6f07b3fc61e4f64c Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Tue, 4 Feb 2020 14:33:46 +1100 Subject: puff: enable PP5000_HDMI and CPU C10 gating TEST=Verified proto can turn off the relevant core rails: * Pretend to be an EVT board: ectool cbi set 0 1 * Reboot EC * Drop to S0ix: echo freeze > /sys/power/state * Verify CPU_C10_GATE is asserted (powerindebug) and EN_S0_RAILS is deasserted (gpioget EN_S0_RAILS) * Wake system and ensure it resumes correctly BUG=b:144719399 BRANCH=None Change-Id: I8e4158ffac38461e8679ac49a084b4296bcef210 Signed-off-by: Peter Marheine Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035432 Reviewed-by: Andrew McRae --- board/puff/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/puff/gpio.inc') diff --git a/board/puff/gpio.inc b/board/puff/gpio.inc index 178553f13b..82f53aa48b 100644 --- a/board/puff/gpio.inc +++ b/board/puff/gpio.inc @@ -30,7 +30,7 @@ GPIO_INT(SLP_S3_L, PIN(A, 5), GPIO_INT_BOTH, power_signal_interrupt) #endif GPIO_INT(PG_PP950_VCCIO_OD, PIN(1, 7), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_S0_L, PIN(D, 5), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(CPU_C10_GATE_L, PIN(6, 7), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(CPU_C10_GATE_L, PIN(6, 7), GPIO_INT_BOTH, c10_gate_interrupt) GPIO_INT(IMVP8_VRRDY_OD, PIN(1, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Other interrupts */ -- cgit v1.2.1