From 62b6c2777c9915723368c0c31df17f7ce30cc7a6 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Fri, 22 May 2020 11:46:27 -0700 Subject: honeybuns: Enable I2C feature and CBI support This CL adds config options and tables required to pull in i2c support for honeybuns. In addition, config options for CBI were added to facilitate i2c testing. BUG=b:148493929 BRANCH=None TEST=ran i2cscan on quiche > i2cscan Scanning 0 usbc................. 0x18. 0x19. 0x1a. 0x1b. 0x1c. 0x1d. 0x1e. 0x1f. 0x20. 0x21. 0x22. 0x23. 0x24. 0x25. 0x26. 0x27........................... 0x42.............................. 0x60....................... Scanning 1 usb_mst. 0x08. 0x09. 0x0a. 0x0b. 0x0c. 0x0d. 0x0e. 0x0f. 0x10. 0x11. 0x12. 0x13. 0x14. 0x15. 0x16. 0x17.......................................... 0x41................................ 0x61......... 0x6a............. Scanning 2 eeprom......................................... 0x30................................ 0x50....................................... Signed-off-by: Scott Collyer Change-Id: Ib1b8b795a2a07a5b1cbe167b17c3f70a8d9703b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213943 Commit-Queue: Scott Collyer Tested-by: Scott Collyer Reviewed-by: Diana Z --- board/quiche/gpio.inc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'board/quiche/gpio.inc') diff --git a/board/quiche/gpio.inc b/board/quiche/gpio.inc index 26b12adfa2..e6264c741e 100644 --- a/board/quiche/gpio.inc +++ b/board/quiche/gpio.inc @@ -45,8 +45,31 @@ GPIO(EC_HUB3_RESET_L, PIN(C, 10), GPIO_ODR_LOW) GPIO(EC_FLASH_WP_ODL, PIN(A, 3), GPIO_ODR_HIGH) GPIO(EC_WP_L, PIN(E, 11), GPIO_INT_BOTH) +/* + * I2C SCL/SDA pins. These will normally be under control of the peripheral from + * alt fucntion setting below. But if a port gets wedged, the unwedge code uses + * these signals as regular GPIOs. + */ +GPIO(EC_I2C1_SCL, PIN(A, 15), GPIO_ODR_HIGH) +GPIO(EC_I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH) +GPIO(EC_I2C2_SDA, PIN(A, 8), GPIO_ODR_HIGH) +GPIO(EC_I2C2_SCL, PIN(A, 9), GPIO_ODR_HIGH) +GPIO(EC_I2C3_SCL, PIN(C, 8), GPIO_ODR_HIGH) +GPIO(EC_I2C3_SDA, PIN(C, 9), GPIO_ODR_HIGH) + /* Unimplemented signals since we are not an EC */ UNIMPLEMENTED(ENTERING_RW) /* USART3_TX/RX GPIOC 10-11*/ ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_UART, GPIO_PULL_UP) +/* I2C Ports + * I2C1: SDA/SCL -> PB7/PA15 + * I2C2: SDA/SCL -> PA8/PA9 + * I2C3: SDA/SCL -> PC8/PC9 + */ +ALTERNATE(PIN_MASK(B, 0x0080), 4, MODULE_I2C, GPIO_OPEN_DRAIN) +ALTERNATE(PIN_MASK(A, 0X8000), 4, MODULE_I2C, GPIO_OPEN_DRAIN) +ALTERNATE(PIN_MASK(A, 0x0300), 4, MODULE_I2C, GPIO_OPEN_DRAIN) +ALTERNATE(PIN_MASK(C, 0x0300), 8, MODULE_I2C, GPIO_OPEN_DRAIN) +/* GPIOA4-7: SPI Signals */ +ALTERNATE(PIN_MASK(A, 0x00F0), 5, MODULE_SPI, 0) -- cgit v1.2.1