From 8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3 Mon Sep 17 00:00:00 2001 From: Vijay Hiremath Date: Thu, 30 May 2019 16:25:15 -0700 Subject: intel_x86/power: Consolidate chipset specific power signals array Currently chipset specific power signals are defined at board/baseboard level. These power signals are moved to chipset specific file to minimize the redundant power signals array defined for each board/baseboard. BUG=b:134079574 BRANCH=none TEST=make buildall -j Change-Id: I351904f7cd2e0f27844c0711beb118d390219581 Signed-off-by: Vijay Hiremath Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837 Reviewed-by: Aseda Aboagye --- board/reef_it8320/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board/reef_it8320/gpio.inc') diff --git a/board/reef_it8320/gpio.inc b/board/reef_it8320/gpio.inc index 6c07d19f38..808787d475 100644 --- a/board/reef_it8320/gpio.inc +++ b/board/reef_it8320/gpio.inc @@ -18,7 +18,7 @@ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_inter #ifdef CONFIG_POWER_S0IX GPIO_INT(PCH_SLP_S0_L, PIN(B, 7), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0_L */ #endif -GPIO_INT(SUSPWRNACK, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRNACK */ +GPIO_INT(SUSPWRDNACK, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SUSPWRNACK */ GPIO_INT(LID_OPEN, PIN(E, 2), GPIO_INT_BOTH, lid_interrupt) /* LID_OPEN */ #ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS GPIO_INT(PCH_PLTRST_L, PIN(E, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lpcrst_interrupt) /* PLT_RST_L */ -- cgit v1.2.1