From c268f2eee300bb56adcf8ff942325469a936a5d6 Mon Sep 17 00:00:00 2001 From: Vincent Palatin Date: Fri, 2 Jan 2015 09:41:34 -0800 Subject: zinger: maintain a 64-bit time counter Keep track of the high 32-bit of the microsecond time counter to avoid rollback issues. Just activate the timer "update" interrupt (aka UIE) and increment the high word on every update interrupt. Also disable STOP mode when we are going to roll-over during sleep to avoid missing the event. Given that's only happening every hour, we should not waste too much power. Signed-off-by: Vincent Palatin BRANCH=samus BUG=chrome-os-partner:34159 TEST=patch the code to set the initial TIM2 value to 0xFC000000, wait for 67s, see the counter rolling and the high word incrementing, then verify that Zinger is still functional. Change-Id: I3a2f8fc09104d8ac75c581b2abcbcef99344def7 Reviewed-on: https://chromium-review.googlesource.com/238220 Trybot-Ready: Vincent Palatin Tested-by: Vincent Palatin Reviewed-by: Alec Berg Commit-Queue: Vincent Palatin --- board/zinger/hardware.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'board/zinger/hardware.c') diff --git a/board/zinger/hardware.c b/board/zinger/hardware.c index 54a92aaccd..1713ca342e 100644 --- a/board/zinger/hardware.c +++ b/board/zinger/hardware.c @@ -146,11 +146,12 @@ static void timers_init(void) /* TIM2 is a 32-bit free running counter with 1Mhz frequency */ STM32_TIM_CR2(2) = 0x0000; STM32_TIM32_ARR(2) = 0xFFFFFFFF; - STM32_TIM32_CNT(2) = 0; STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1; STM32_TIM_EGR(2) = 0x0001; /* Reload the pre-scaler */ STM32_TIM_CR1(2) = 1; - STM32_TIM_DIER(2) = 0; + STM32_TIM32_CNT(2) = 0x00000000; + STM32_TIM_SR(2) = 0; /* Clear pending interrupts */ + STM32_TIM_DIER(2) = 1; /* Overflow interrupt */ task_enable_irq(STM32_IRQ_TIM2); } -- cgit v1.2.1