From e37b18d7d1d87bd77ace5b9bc86c4dd58624195c Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Mon, 6 Jun 2016 19:49:15 -0700 Subject: reef: Initialize EC_PCH_PWROK low The PCH_PWROK signal has a pull-up on the PCH side, so we really want to drive this low. BUG=none BRANCH=none TEST=none Change-Id: Icb0702916671cfd632e67d036bfb865e968c102c Signed-off-by: David Hendricks Reviewed-on: https://chromium-review.googlesource.com/350201 Reviewed-by: Shawn N --- board/reef/gpio.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'board') diff --git a/board/reef/gpio.inc b/board/reef/gpio.inc index f26bbfaabe..1c69b0ef8f 100644 --- a/board/reef/gpio.inc +++ b/board/reef/gpio.inc @@ -87,7 +87,7 @@ GPIO(PP3300_PG, PIN(6, 2), GPIO_INPUT) GPIO(EN_PP5000, PIN(C, 6), GPIO_OUT_LOW) GPIO(PP5000_PG, PIN(7, 1), GPIO_INPUT) GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 2), GPIO_ODR_HIGH) -GPIO(PCH_SYS_PWROK, PIN(E, 7), GPIO_OUTPUT) /* EC_PCH_PWROK_OD */ +GPIO(PCH_SYS_PWROK, PIN(E, 7), GPIO_OUT_LOW) /* EC_PCH_PWROK */ GPIO(ENABLE_BACKLIGHT, PIN(9, 7), GPIO_ODR_HIGH | GPIO_SEL_1P8V) /* EC_BL_EN_OD */ GPIO(WIRELESS_GPIO_WLAN_POWER, PIN(6, 6), GPIO_ODR_HIGH) /* EN_PP3300_WLAN_ODL */ -- cgit v1.2.1