From 014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4 Mon Sep 17 00:00:00 2001 From: "Hu, Hebo" Date: Wed, 20 Mar 2019 19:13:37 +0800 Subject: ish/ish5: implement AON low power mode (D0i1-3) 1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented 2: D0i3 (TCG + SRAM power off) implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c Signed-off-by: Hu, Hebo Reviewed-on: https://chromium-review.googlesource.com/1531772 Commit-Ready: Hebo Hu Tested-by: Jett Rink Reviewed-by: Jett Rink Reviewed-by: Hebo Hu --- chip/ish/config_chip.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'chip/ish/config_chip.h') diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h index 93cc527f6b..74432baca1 100644 --- a/chip/ish/config_chip.h +++ b/chip/ish/config_chip.h @@ -58,6 +58,10 @@ #define CONFIG_ISH_AON_SRAM_ROM_START (CONFIG_ISH_AON_SRAM_BASE_END - \ CONFIG_ISH_AON_SRAM_ROM_SIZE) +#define CONFIG_ISH_SRAM_BANK_SIZE 0x8000 +#define CONFIG_ISH_SRAM_BANKS (CONFIG_ISH_SRAM_SIZE / \ + CONFIG_ISH_SRAM_BANK_SIZE) + /* Required for panic_output */ #define CONFIG_RAM_SIZE CONFIG_ISH_SRAM_SIZE #define CONFIG_RAM_BASE CONFIG_ISH_SRAM_BASE_START -- cgit v1.2.1