From 3c53f0413a966da25cbe803f614acd36d5c87685 Mon Sep 17 00:00:00 2001 From: Scott Collyer Date: Thu, 16 Aug 2018 08:41:50 -0700 Subject: ite: Add support for 3rd Type C port in bbram DragonEgg has 3 Type C ports and needs BRAM_IDX_PD2 as only 2 ports were supproted previously. BUG=b:111281797 BRANCH=none TEST=Verfied that error messages from invalid bram_idx went away. Change-Id: I242850a89413f0a573155e5e325f4e0a540d33e6 Signed-off-by: Scott Collyer Reviewed-on: https://chromium-review.googlesource.com/1178996 Commit-Ready: ChromeOS CL Exonerator Bot Tested-by: Scott Collyer Reviewed-by: Furquan Shaikh Reviewed-by: Jett Rink --- chip/it83xx/registers.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'chip/it83xx/registers.h') diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 57d73f7a26..cd7fcc0c2a 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1105,11 +1105,12 @@ enum bram_indices { BRAM_IDX_RESET_FLAGS2 = 2, BRAM_IDX_RESET_FLAGS3 = 3, - /* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 2 bytes */ + /* PD state data for CONFIG_USB_PD_DUAL_ROLE uses 1 byte per port */ BRAM_IDX_PD0 = 4, BRAM_IDX_PD1 = 5, + BRAM_IDX_PD2 = 6, - /* index 6 ~ 7 are reserved */ + /* index 7 is reserved */ BRAM_IDX_SCRATCHPAD0 = 8, BRAM_IDX_SCRATCHPAD1 = 9, -- cgit v1.2.1