From 8a6674329235c0446aa1ce8b7ac36371c40308fe Mon Sep 17 00:00:00 2001 From: Dino Li Date: Wed, 18 Jul 2018 17:42:21 +0800 Subject: IT8320DX: espi: reset espi module by FW There is a bug on DX's espi_reset# pin. So we can't enable hardware mechanism of espi_reset#. To workaround this issue, this CL introduces a new macro to config_chip.h IT83XX_ESPI_RESET_MODULE_BY_FW which is defined when CHIP_VRAIANT is IT8320DX. When this macro is defined, the epsi hw reset pin function is disabled. Instead, the interrupt handler for this espi reset pin uses the GCTRL_RSTS register to force a reset of VCC domain logic in the EC which resets the eSPI and LPC modules. BUG=b:111480168 BRANCH=none TEST=The eSPI module is reset when EC's espi_reset# pin is asserted. Change-Id: Id7dfe746e7463c95735dde9a17777f3fce1030d0 Signed-off-by: Dino Li Reviewed-on: https://chromium-review.googlesource.com/1138134 Commit-Ready: Scott Collyer Tested-by: Scott Collyer Reviewed-by: Jett Rink --- chip/it83xx/registers.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'chip/it83xx/registers.h') diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index b91c18817e..227cdc2f99 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -538,6 +538,10 @@ #define IT83XX_GPIO_BASE 0x00F01600 #define IT83XX_GPIO_GCR REG8(IT83XX_GPIO_BASE+0x00) +#define IT83XX_GPIO_GCR_LPC_RST_B7 0x1 +#define IT83XX_GPIO_GCR_LPC_RST_D2 0x2 +#define IT83XX_GPIO_GCR_LPC_RST_DISABLE 0x3 +#define IT83XX_GPIO_GCR_LPC_RST_POS 1 #define IT83XX_GPIO_GPDRA REG8(IT83XX_GPIO_BASE+0x01) #define IT83XX_GPIO_GPDRB REG8(IT83XX_GPIO_BASE+0x02) -- cgit v1.2.1