From 74615c1011382d930f3c4be72ec043ad35856b95 Mon Sep 17 00:00:00 2001 From: Archana Patni Date: Wed, 17 Feb 2016 16:18:15 +0530 Subject: skylake: do not clear masks in S0ix -> S0 transition EC clears the SCI/SMI/Wake masks in the resume sequence for S3 and S0ix. This works in the S3 case because Coreboot reprograms the masks after EC. But in S0ix, these masks stay cleared forever. This means that no further events are sent to the host. This patch conditionally clears the masks only in the S3 transition. BRANCH=glados BUG=chrome-os-partner:48834 TEST=hostevent in EC console before and after S0ix to ensure SCI masks are preserved Change-Id: I23751680788ee7a239e321309a1334d37adc4f43 Signed-off-by: Archana Patni Signed-off-by: Subramony Sesha Signed-off-by: Jenny TC Reviewed-on: https://chromium-review.googlesource.com/320191 Commit-Ready: Jenny Tc Tested-by: Jenny Tc Reviewed-by: Shawn N --- chip/mec1322/lpc.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'chip/mec1322') diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index a53a02efad..e58d7138ff 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -294,11 +294,15 @@ DECLARE_HOOK(HOOK_CHIPSET_STARTUP, setup_lpc, HOOK_PRIO_FIRST); static void lpc_resume(void) { - /* Mask all host events until the host unmasks them itself. */ - lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); - lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); - +#ifdef CONFIG_POWER_S0IX + if (chipset_in_state(CHIPSET_STATE_SUSPEND | CHIPSET_STATE_ON)) +#endif + { + /* Mask all host events until the host unmasks them itself. */ + lpc_set_host_event_mask(LPC_HOST_EVENT_SMI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_SCI, 0); + lpc_set_host_event_mask(LPC_HOST_EVENT_WAKE, 0); + } /* Store port 80 event so we know where resume happened */ port_80_write(PORT_80_EVENT_RESUME); } -- cgit v1.2.1