From 0542741e0e8727ae53bce47a1fd4459735056b53 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Mon, 21 Sep 2020 11:13:33 +0800 Subject: it83xx: read_clear_int_mask() read and clear interrupt bit. This change pulled the operation of interrupt disable into read_clear_int_mask(). Because riscv core supports instruction csrrc to atomic read and clear bit in CSR register. With this change, we won't need to separate operations of reading and clearing interrupt bit on riscv core. BUG=none BRANCH=none TEST=read_clear_int_mask() is able to disable interrupt and return saved interrupt bit on both nds32 and riscv cores. Signed-off-by: Dino Li Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739 Reviewed-by: Jett Rink --- chip/mt8192_scp/ipi.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'chip/mt8192_scp') diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c index 83d9fa8ebb..4081e47075 100644 --- a/chip/mt8192_scp/ipi.c +++ b/chip/mt8192_scp/ipi.c @@ -30,10 +30,8 @@ static uint32_t disable_irq_count, saved_int_mask; void ipi_disable_irq(void) { - if (atomic_inc(&disable_irq_count, 1) == 0) { - saved_int_mask = get_int_mask(); - interrupt_disable(); - } + if (atomic_inc(&disable_irq_count, 1) == 0) + saved_int_mask = read_clear_int_mask(); } void ipi_enable_irq(void) -- cgit v1.2.1