From f9c201e93c45f008b79ce63c1ec276ede05146f0 Mon Sep 17 00:00:00 2001 From: Mulin Chao Date: Fri, 5 May 2017 17:38:56 +0800 Subject: npcx: flash: Add write-protect support for internal flash of npcx7 ec In order to support write-protect mechanism for the internal flash of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by controlling the WP_L pin of internal flash. During ec initialization or any utilities related to access status registers, we'll protect them if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we only can unlock write protection of internal flash by rebooting ec. This CL also includes: 1. Add protect_range array of npcx7's internal flash (W25Q80) for write-protect mechanism. 2. Add bypass of bit 7 of DEVCNT. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. (Besides gru) Build poppy board and upload FW to platform. No issues found. Passed flash write-protect checking on npcx796f evb. Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2 Signed-off-by: Mulin Chao Reviewed-on: https://chromium-review.googlesource.com/501727 Reviewed-by: Randall Spangler --- chip/npcx/gpio.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'chip/npcx/gpio.c') diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index db9be12b1d..1b32297013 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -360,6 +360,14 @@ void gpio_pre_init(void) int flags; int i, j; +#ifdef CHIP_FAMILY_NPCX7 + /* + * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata + * for more information. It will be fixed in next chip. + */ + SET_BIT(NPCX_DEVCNT, 7); +#endif + /* Pin_Mux for FIU/SPI (set to GPIO) */ SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_GPIO_NO_SPIP); SET_BIT(NPCX_DEVALT(0), NPCX_DEVALT0_NO_F_SPI); -- cgit v1.2.1