From 52d333662a1d463223bcee4792cc7abd3e3482d6 Mon Sep 17 00:00:00 2001 From: CHLin Date: Mon, 9 Jan 2017 14:55:20 +0800 Subject: npcx: shi: fix bug of clearing EVSTAT_EOR bit It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit in a register. It will also clear other bits if they are also set. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall; boot up on gru, run ectool stress test for a while without problem. Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f Signed-off-by: CHLin Reviewed-on: https://chromium-review.googlesource.com/425589 Commit-Ready: CH Lin Tested-by: CH Lin Reviewed-by: Shawn N --- chip/npcx/shi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'chip/npcx/shi.c') diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 0e1b8b608d..9c5aec1f56 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -687,7 +687,7 @@ void shi_cs_event(enum gpio_signal signal) * Clear possible EOR event from previous transaction since it's * irrelevant now that CS is re-asserted. */ - SET_BIT(NPCX_EVSTAT, NPCX_EVSTAT_EOR); + NPCX_EVSTAT = 1 << NPCX_EVSTAT_EOR; /* * Enable SHI interrupt - we will either succeed to parse our host -- cgit v1.2.1