From 9ab83ede1016637429ac66140d7c903a0dfaefd9 Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Fri, 5 Aug 2016 00:28:09 -0700 Subject: npcx: Adjust relative IRQ priorities for high-priority UART Our UART interrupt must be able to preempt our SHI_CS interrupt, otherwise console input may be lost. Adjust our relative IRQ priorities to accommodate this. BUG=chrome-os-partner:55920 BRANCH=None TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from the recovery screen, verify that all input is received by the EC. Change-Id: I36203511f5883272287ac22d0704098fbd933758 Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/366622 Commit-Ready: Shawn N Tested-by: Mulin Chao Reviewed-by: Aseda Aboagye Reviewed-by: Mulin Chao --- chip/npcx/shi.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'chip/npcx/shi.c') diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 416ebc3902..6cf030cf7c 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -650,11 +650,7 @@ void shi_int_handler(void) log_unexpected_state("IBF"); } } -/* - * The interrupt priority for SHI interrupt should be higher than - * GPIO. Then we could receive CS-deasserted event even in CS-asserted ISR. - */ -DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 0); +DECLARE_IRQ(NPCX_IRQ_SHI, shi_int_handler, 1); /* Handle an CS assert event on the SHI_CS_L pin */ void shi_cs_event(enum gpio_signal signal) -- cgit v1.2.1