From d58e54730c03290296df5bb65cb84264e4b2facc Mon Sep 17 00:00:00 2001 From: Shawn Nematbakhsh Date: Fri, 4 Sep 2015 19:09:33 -0700 Subject: cleanup: Rename geometry constants Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N Tested-by: Shawn N Reviewed-by: Randall Spangler --- chip/stm32/flash-f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'chip/stm32/flash-f.c') diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index a1d148a104..c57f072fc2 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -205,7 +205,7 @@ static int write_optb(int byte, uint8_t value) int flash_physical_write(int offset, int size, const char *data) { - uint16_t *address = (uint16_t *)(CONFIG_FLASH_BASE + offset); + uint16_t *address = (uint16_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset); int res = EC_SUCCESS; int i; @@ -285,7 +285,7 @@ int flash_physical_erase(int offset, int size) continue; /* select page to erase */ - STM32_FLASH_AR = CONFIG_FLASH_BASE + offset; + STM32_FLASH_AR = CONFIG_PROGRAM_MEMORY_BASE + offset; /* set STRT bit : start erase */ STM32_FLASH_CR |= STRT; -- cgit v1.2.1