From 049463f8ad985f9cb996caa7dbc5438383bd3084 Mon Sep 17 00:00:00 2001 From: Vic Yang Date: Wed, 4 Feb 2015 11:28:53 -0800 Subject: stm32: Add delay after enabling peripheral clock We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg Reviewed-by: Randall Spangler Tested-by: Vic Yang Commit-Queue: Vic Yang --- chip/stm32/hwtimer32.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'chip/stm32/hwtimer32.c') diff --git a/chip/stm32/hwtimer32.c b/chip/stm32/hwtimer32.c index 4dc4c8cdb7..691e2f90f7 100644 --- a/chip/stm32/hwtimer32.c +++ b/chip/stm32/hwtimer32.c @@ -148,6 +148,8 @@ int __hw_clock_source_init(uint32_t start_t) { /* Enable TIM peripheral block clocks */ __hw_timer_enable_clock(TIM_CLOCK32, 1); + /* Delay 1 APB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_APB, 1); /* * Timer configuration : Upcounter, counter disabled, update event only @@ -218,6 +220,8 @@ void hwtimer_setup_watchdog(void) { /* Enable clock */ __hw_timer_enable_clock(TIM_WATCHDOG, 1); + /* Delay 1 APB clock cycle after the clock is enabled */ + clock_wait_bus_cycles(BUS_APB, 1); /* * Timer configuration : Up counter, counter disabled, update -- cgit v1.2.1