From 608fa5efd868325ce85fca1f777a89c0909ea032 Mon Sep 17 00:00:00 2001 From: Alec Berg Date: Thu, 21 May 2015 13:29:03 -0700 Subject: stm32f0: i2c: fix master i2c sending partial transfers Fix master i2c when sending partial transfers using I2C_XFER_START and I2C_XFER_STOP. BUG=none BRANCH=none TEST=Tested i2c transfers on oak. tested transfers with I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) and tested partial transfers with just one flag. For partial transfers I tested two different types: - i2c_xfer START only transmitting, then another i2c_xfer with more trasnmitting followed by a STOP. verified with logic analyzer that there is not restart in the middle. - i2c_xfer START with transmitting and receiving, then another i2c_xfer with more receiving followed by a STOP. verified with logic analyzer that there is one restart in between transmitting and receving and no restart in between the two calls to i2c_xfer. Change-Id: Ie4146d1cf7d39f7dc56fd02e65add6bf02772e67 Signed-off-by: Alec Berg Reviewed-on: https://chromium-review.googlesource.com/272690 Reviewed-by: Vincent Palatin --- chip/stm32/registers.h | 1 + 1 file changed, 1 insertion(+) (limited to 'chip/stm32/registers.h') diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 52c74ef64f..f9ff3d1c69 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -474,6 +474,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_I2C_ISR_NACK (1 << 4) #define STM32_I2C_ISR_STOP (1 << 5) #define STM32_I2C_ISR_TC (1 << 6) +#define STM32_I2C_ISR_TCR (1 << 7) #define STM32_I2C_ISR_BERR (1 << 8) #define STM32_I2C_ISR_ARLO (1 << 9) #define STM32_I2C_ISR_OVR (1 << 10) -- cgit v1.2.1