From ac77140b7f4f42075d2377fc9d956a636b05aacf Mon Sep 17 00:00:00 2001 From: Gwendal Grignou Date: Mon, 11 Mar 2019 16:07:55 -0700 Subject: common: bit change 1 << constants with BIT(constants) Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri --- chip/stm32/clock-stm32h7.c | 2 +- chip/stm32/clock-stm32l.c | 4 +- chip/stm32/clock-stm32l4.c | 4 +- chip/stm32/config_chip.h | 2 +- chip/stm32/dma.c | 2 +- chip/stm32/flash-f.c | 2 +- chip/stm32/flash-stm32f0.c | 2 +- chip/stm32/flash-stm32f3.c | 2 +- chip/stm32/flash-stm32h7.c | 4 +- chip/stm32/flash-stm32l.c | 4 +- chip/stm32/pwm.c | 6 +- chip/stm32/usb_dwc_registers.h | 142 ++++++++++++++++++++--------------------- 12 files changed, 88 insertions(+), 88 deletions(-) (limited to 'chip/stm32') diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 30faa0035a..44d6e2e55a 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -32,7 +32,7 @@ * with /4 prescaler (2^2): period 125 us, full range ~8s */ #define LPTIM_PRESCALER_LOG2 2 -#define LPTIM_PRESCALER (1 << LPTIM_PRESCALER_LOG2) +#define LPTIM_PRESCALER BIT(LPTIM_PRESCALER_LOG2) #define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER)) /* diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index b0903b5cb1..2409e7918d 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -211,9 +211,9 @@ void clock_enable_module(enum module_id module, int enable) int new_mask; if (enable) - new_mask = clock_mask | (1 << module); + new_mask = clock_mask | BIT(module); else - new_mask = clock_mask & ~(1 << module); + new_mask = clock_mask & ~BIT(module); /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index c9042d10c4..182abcafca 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -324,9 +324,9 @@ void clock_enable_module(enum module_id module, int enable) int new_mask; if (enable) - new_mask = clock_mask | (1 << module); + new_mask = clock_mask | BIT(module); else - new_mask = clock_mask & ~(1 << module); + new_mask = clock_mask & ~BIT(module); /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 0305197996..99cbd9b2be 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -140,7 +140,7 @@ #define CONFIG_CHIP_PRE_INIT #define GPIO_NAME_BY_PIN(port, index) #port#index -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) /* Prescaler values for PLL. Currently used only by STM32L476. */ diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index 26dfa0f823..e18676876f 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -65,7 +65,7 @@ void dma_select_channel(enum dma_channel channel, unsigned char stream) /* Local channel # starting from 0 on each DMA controller */ const unsigned char ch = channel % STM32_DMAC_PER_CTLR; const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL; - const unsigned char mask = (1 << shift) - 1; + const unsigned char mask = BIT(shift) - 1; uint32_t val; ASSERT(ch < STM32_DMAC_PER_CTLR); diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index aaf8e69873..8518485caa 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -442,7 +442,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags) #endif if (protect) - val &= ~(1 << block); + val &= ~BIT(block); else val |= 1 << block; } diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index 6472b3e23b..e2ff2c779c 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -15,7 +15,7 @@ int flash_physical_get_protect(int block) { - return !(STM32_FLASH_WRPR & (1 << block)); + return !(STM32_FLASH_WRPR & BIT(block)); } /* diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index 843bbf48e4..ab505a082b 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -88,7 +88,7 @@ int flash_physical_get_protect(int block) { return (entire_flash_locked || #if defined(CHIP_FAMILY_STM32F3) - !(STM32_FLASH_WRPR & (1 << block)) + !(STM32_FLASH_WRPR & BIT(block)) #elif defined(CHIP_FAMILY_STM32F4) !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) #endif diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index 0f82bf409a..ba0a8a69f1 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -46,7 +46,7 @@ */ #define HWBANK_SIZE (CONFIG_FLASH_SIZE / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) -#define BLOCKS_HWBANK_MASK ((1 << BLOCKS_PER_HWBANK) - 1) +#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) /* * We can tune the power consumption vs erase/write speed @@ -358,7 +358,7 @@ int flash_physical_get_protect(int block) int bank = block / BLOCKS_PER_HWBANK; int index = block % BLOCKS_PER_HWBANK; - return !(STM32_FLASH_WPSN_CUR(bank) & (1 << index)); + return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index)); } /* diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index f796f4efaa..61916abf2d 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -314,13 +314,13 @@ int flash_physical_get_protect(int block) return 1; /* Check the active write protect status */ - return STM32_FLASH_WRPR & (1 << block); + return STM32_FLASH_WRPR & BIT(block); } int flash_physical_protect_at_boot(uint32_t new_flags) { uint32_t prot; - uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; + uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; int rv; if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index 45d489a8c0..123c09968a 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -43,7 +43,7 @@ static void pwm_configure(enum pwm_channel ch) int frequency = pwm->frequency ? pwm->frequency : 100; uint16_t ccer; - if (using_pwm & (1 << ch)) + if (using_pwm & BIT(ch)) return; /* Enable timer */ @@ -109,7 +109,7 @@ static void pwm_disable(enum pwm_channel ch) const struct pwm_t *pwm = pwm_channels + ch; timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - if ((using_pwm & (1 << ch)) == 0) + if ((using_pwm & BIT(ch)) == 0) return; /* Main output disable */ @@ -141,7 +141,7 @@ void pwm_enable(enum pwm_channel ch, int enabled) int pwm_get_enabled(enum pwm_channel ch) { - return using_pwm & (1 << ch); + return using_pwm & BIT(ch); } static void pwm_reconfigure(enum pwm_channel ch) diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index f8b90c1d1f..faac9ca775 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -175,13 +175,13 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) #define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) -#define GOTGCTL_BVALOEN (1 << GC_USB_GOTGCTL_BVALIDOVEN_LSB) +#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) #define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ -#define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) /* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) /* HS Burst Len */ #define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) /* Bit 7 */ @@ -194,7 +194,7 @@ extern struct dwc_usb usb_ctl; #define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ -#define GUSBCFG_FDMOD (1 << GC_USB_GUSBCFG_FDMOD_LSB) +#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) #define GUSBCFG_PHYSEL BIT(6) #define GUSBCFG_SRPCAP BIT(8) #define GUSBCFG_HNPCAP BIT(9) @@ -210,81 +210,81 @@ extern struct dwc_usb usb_ctl; #define GUSBCFG_TSDPS BIT(22) -#define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE (1 << GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH (1 << GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH (1 << GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) #define GRSTCTL_TXFNUM(n) \ (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) #define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI (1 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVADDR(a) \ (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK (1 << GC_USB_DCFG_NZSTSOUTHSHK_LSB) +#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) -#define DCTL_SFTDISCON (1 << GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK (1 << GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK (1 << GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE (1 << GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK (1 << GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK (1 << GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK (1 << GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK (1 << GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK (1 << GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK (1 << GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK (1 << GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK (1 << GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK (1 << GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK (1 << GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK (1 << GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK (1 << GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK (1 << GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK (1 << GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK (1 << GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK (1 << GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK (1 << GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK (1 << GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK (1 << GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK (1 << GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK (1 << GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR (1 << GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR (1 << GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR (1 << GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD (1 << GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF (1 << GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS (1 << GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP (1 << GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT (1 << GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT (1 << GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS (1 << GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT (1 << GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP (1 << GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN (1 << GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL (1 << GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR (1 << GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP (1 << GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR (1 << GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR (1 << GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD (1 << GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT (1 << GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT (1 << GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR (1 << GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS (1 << GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS (1 << GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP (1 << GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD (1 << GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD (1 << GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL (1 << GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) #define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) @@ -292,14 +292,14 @@ extern struct dwc_usb usb_ctl; #define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK #define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL (1 << GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK (1 << GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID (1 << GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK (1 << GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS (1 << GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA (1 << GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS (1 << GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) -- cgit v1.2.1