From c55f09496009249426574e1facf96a222b4e4693 Mon Sep 17 00:00:00 2001 From: Vincent Palatin Date: Wed, 28 Feb 2018 09:34:17 +0100 Subject: stm32: fix RTC configuration on STM32H7 The DBP bit needs to be set in the PWR_CR1 register before doing the RTC configuration (in order to be able to right RTC registers). Signed-off-by: Vincent Palatin BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, dump the RTC_TR register and it is incrementing every second, e.g. 'rw 0x58004000'. Change-Id: I02dc6c6f1852ced934bccf3e401f4fdc1aad57d9 Reviewed-on: https://chromium-review.googlesource.com/941224 Commit-Ready: Vincent Palatin Tested-by: Vincent Palatin Reviewed-by: Aseda Aboagye --- chip/stm32/system.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'chip') diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 396fcac964..4a5927d90c 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -268,14 +268,12 @@ void system_pre_init(void) #endif /* Delay 1 APB clock cycle after the clock is enabled */ clock_wait_bus_cycles(BUS_APB, 1); -#ifndef CHIP_FAMILY_STM32H7 /* Enable access to RCC CSR register and RTC backup registers */ STM32_PWR_CR |= 1 << 8; #ifdef CHIP_VARIANT_STM32L476 /* Enable Vddio2 */ STM32_PWR_CR2 |= 1 << 9; #endif -#endif /* !CHIP_FAMILY_STM32H7 */ /* switch on LSI */ STM32_RCC_CSR |= 1 << 0; -- cgit v1.2.1