From e82fb744a9596e411d568926e27640c4494f547e Mon Sep 17 00:00:00 2001 From: Dino Li Date: Mon, 17 Oct 2022 17:05:41 +0800 Subject: it83xx: espi: reset pltrst# virtual wire signal during espi reset EC software reset doesn't reset pltrst# by default. This change was made to reset pltrst# during espi reset. So Ampton won't get stuck after watchdog reset. BRANCH=octopus BUG=b:235443631 TEST=Ampton won't get stuck after watchdog reset. Signed-off-by: Dino Li Change-Id: Ice77a902185046757d6b7bc70edee53eb81e64dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3959261 Commit-Queue: Henry Sun Reviewed-by: luluboy luluboys Reviewed-by: Diana Z Tested-by: Luluboy Jian Tested-by: luluboy luluboys Reviewed-by: Luluboy Jian --- chip/it83xx/clock.c | 3 +++ chip/it83xx/registers.h | 2 ++ 2 files changed, 5 insertions(+) (limited to 'chip') diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index ab1da3b68a..fccc62eee7 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -301,7 +301,10 @@ void clock_init(void) * version, so we have to reset eSPI configurations during init to * ensure Host and EC are synchronized (especially for the field of * I/O mode) + * Since bit4 of VWCTRL2 register is enabled, the below reset routine + * will be able to reset pltrst# signal. */ + IT83XX_ESPI_VWCTRL2 |= ESPI_PLTRST_ESPI_RESET; if (!system_jumped_to_this_image()) espi_fw_reset_module(); #endif diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 025daeb61a..ade0b97289 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1650,6 +1650,8 @@ enum i2c_channels { #define IT83XX_ESPI_VWCTRL1 REG8(IT83XX_ESPI_VW_BASE + 0x91) #define IT83XX_ESPI_VWCTRL2 REG8(IT83XX_ESPI_VW_BASE + 0x92) #define IT83XX_ESPI_VWCTRL3 REG8(IT83XX_ESPI_VW_BASE + 0x93) +/* 1b: Refers to espi_reset# for pltrst */ +#define ESPI_PLTRST_ESPI_RESET BIT(4) /* eSPI Queue 0 */ #define IT83XX_ESPI_QUEUE_BASE 0x00F03300 -- cgit v1.2.1