From b011985e89d9d2e6fceb8ca4dc91bfb8fea52e3d Mon Sep 17 00:00:00 2001 From: Ethan Huang Date: Thu, 1 Jul 2021 16:54:39 +0800 Subject: cortex-m/ec.lds.S: Add padding to manage RW image size For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431 used in Munna), RW image size is not always 8-byte alignment which leads to the failure from flash_range_ok and therefore "EC sync update RW proecess" fails. Here is the proposal of RW image size alignment with CONFIG_FLASH_WRITE_SIZE. 1. Add output section .rw_image_size_alignment for padding 2. Expose new __image_size for hash afterward 3. Make output senction .rw_image_size_alignment !CONFIG_CHIP_INIT_ROM_REGION guarded BRANCH=main BUG=b:188117811 TEST=make buildall + checking symbols (execpt __image_size) listed in ec.R{O,R}.smap for all boards stay the same Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416 Signed-off-by: Ethan Huang Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357 Reviewed-by: Eric Yilun Lin --- core/cortex-m/ec.lds.S | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'core/cortex-m/ec.lds.S') diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index c2c3ea12a3..7b08be81a6 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -500,7 +500,18 @@ SECTIONS */ __flash_used = FLASH_USED_END - ORIGIN(EC_IMAGE_LMA_MEM_REGION); #ifndef CONFIG_CHIP_INIT_ROM_REGION +#if !(defined(SECTION_IS_RW) && (CONFIG_FLASH_WRITE_SIZE > 4)) __image_size = __flash_used; +#else + .rw_image_size_alignment : + { + . = ORIGIN(FLASH) + __flash_used; + BYTE(0xFF); + . = ALIGN (CONFIG_FLASH_WRITE_SIZE); + } > FLASH = 0xFF + + __image_size = __flash_used + SIZEOF(.rw_image_size_alignment); +#endif #endif /* CONFIG_CHIP_INIT_ROM_REGION */ #ifdef CONFIG_FLASH_CROS -- cgit v1.2.1