From 0f73a129b42acfcad843203b602fbbcc8894c614 Mon Sep 17 00:00:00 2001 From: Vincent Palatin Date: Sat, 1 Mar 2014 10:20:47 -0800 Subject: Add Cortex-M0 core support The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin Commit-Queue: Vincent Palatin Tested-by: Vincent Palatin --- core/cortex-m0/thumb_case.S | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 core/cortex-m0/thumb_case.S (limited to 'core/cortex-m0/thumb_case.S') diff --git a/core/cortex-m0/thumb_case.S b/core/cortex-m0/thumb_case.S new file mode 100644 index 0000000000..1229988d9f --- /dev/null +++ b/core/cortex-m0/thumb_case.S @@ -0,0 +1,35 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Thumb mode toolchain helpers for compact switch/case statement. + */ + +#include "config.h" + +.text + +.syntax unified +.code 16 + +/* + * Helper for compact switch + * + * r0: the table index + * lr: the table base address + * + * r0 and lr must be PRESERVED. + * r12 can be clobbered. + */ +.global __gnu_thumb1_case_uqi +.thumb_func +__gnu_thumb1_case_uqi: + push {r1} + mov r1, lr + lsrs r1, r1, #1 + lsls r1, r1, #1 + ldrb r1, [r1, r0] + lsls r1, r1, #1 + add lr, lr, r1 + pop {r1} + bx lr -- cgit v1.2.1