From 30fcb4251724e2db3c69425f441c9ffaf7d2a3d7 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:43:01 -0600 Subject: core/cortex-m0/atomic.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I6476e2382f5f8a74b1e30380b9003d94a33e722a Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729828 Reviewed-by: Jeremy Bettis --- core/cortex-m0/atomic.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'core/cortex-m0') diff --git a/core/cortex-m0/atomic.h b/core/cortex-m0/atomic.h index 7ec856ed62..88b19bf534 100644 --- a/core/cortex-m0/atomic.h +++ b/core/cortex-m0/atomic.h @@ -16,22 +16,22 @@ * * There is no load/store exclusive on ARMv6-M, just disable interrupts */ -#define ATOMIC_OP(asm_op, a, v) \ -({ \ - uint32_t reg0, reg1; \ - \ - __asm__ __volatile__(".syntax unified\n" \ - " cpsid i\n" \ - " ldr %0, [%2]\n" \ - " mov %1, %0\n" \ - #asm_op" %0, %0, %3\n" \ - " str %0, [%2]\n" \ - " cpsie i\n" \ - : "=&l"(reg0), "=&l"(reg1) \ - : "l"(a), "r"(v) \ - : "cc", "memory"); \ - reg1; \ -}) +#define ATOMIC_OP(asm_op, a, v) \ + ({ \ + uint32_t reg0, reg1; \ + \ + __asm__ __volatile__(".syntax unified\n" \ + " cpsid i\n" \ + " ldr %0, [%2]\n" \ + " mov %1, %0\n" #asm_op \ + " %0, %0, %3\n" \ + " str %0, [%2]\n" \ + " cpsie i\n" \ + : "=&l"(reg0), "=&l"(reg1) \ + : "l"(a), "r"(v) \ + : "cc", "memory"); \ + reg1; \ + }) static inline atomic_val_t atomic_clear_bits(atomic_t *addr, atomic_val_t bits) { @@ -62,8 +62,8 @@ static inline atomic_val_t atomic_clear(atomic_t *addr) " ldr %0, [%1]\n" " str %2, [%1]\n" " cpsie i\n" - : "=&l" (ret) - : "l" (addr), "r" (0) + : "=&l"(ret) + : "l"(addr), "r"(0) : "cc", "memory"); return ret; @@ -74,4 +74,4 @@ static inline atomic_val_t atomic_and(atomic_t *addr, atomic_val_t bits) return ATOMIC_OP(ands, addr, bits); } -#endif /* __CROS_EC_ATOMIC_H */ +#endif /* __CROS_EC_ATOMIC_H */ -- cgit v1.2.1