From 014b6c86dfd1aa9ec9ffaba2647d4ca89baf1ef4 Mon Sep 17 00:00:00 2001 From: "Hu, Hebo" Date: Wed, 20 Mar 2019 19:13:37 +0800 Subject: ish/ish5: implement AON low power mode (D0i1-3) 1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented 2: D0i3 (TCG + SRAM power off) implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c Signed-off-by: Hu, Hebo Reviewed-on: https://chromium-review.googlesource.com/1531772 Commit-Ready: Hebo Hu Tested-by: Jett Rink Reviewed-by: Jett Rink Reviewed-by: Hebo Hu --- core/minute-ia/ec.lds.S | 13 +++++++++++++ core/minute-ia/init.S | 2 +- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'core') diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S index f08131092b..8087f7ce01 100644 --- a/core/minute-ia/ec.lds.S +++ b/core/minute-ia/ec.lds.S @@ -13,6 +13,8 @@ SECTIONS { . = CONFIG_ISH_BOOT_START; /* ISH SRAM (640KB) begins at 0xFF000000 */ + __aon_ro_start = .; + /* .init section should be first, since it contains the boot code */ .init : { *(.init*); } .text : { *(.text.*); } @@ -140,6 +142,15 @@ SECTIONS KEEP(*(.rodata.*)) } + /* + * ISH DMA need 64 bytes address align, in D0i3 low power state + * need copy RW part to IMR DDR via DMA + */ + . = ALIGN(64); + __aon_ro_end = .; + + __aon_rw_start = .; + .data : { __data_start = .; *(.data.*); @@ -178,6 +189,8 @@ SECTIONS __shared_mem_buf = .; } + __aon_rw_end = . + CONFIG_SHAREDMEM_MINIMUM_SIZE; + ASSERT((__shared_mem_buf + CONFIG_SHAREDMEM_MINIMUM_SIZE) <= (CONFIG_RAM_BASE + CONFIG_RAM_SIZE), "Not enough space for shared memory.") diff --git a/core/minute-ia/init.S b/core/minute-ia/init.S index 66154b2c19..b8e51ccc91 100644 --- a/core/minute-ia/init.S +++ b/core/minute-ia/init.S @@ -21,7 +21,7 @@ # and hence the same segment selector .set code_seg, 0x8 -.section .text.vecttable +.section .data.vecttable # Macro that defines an interrupt descriptor .macro interrupt_descriptor -- cgit v1.2.1