From 432ea75d92f58e8e31fadb8789c71f49769d467d Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Mon, 7 Dec 2015 18:27:12 -0800 Subject: cr50: add ability to include two identical RW sections in the EC image A typical EC image includes two similar in their functionality subsections, RO and RW. CR50 has a small RO subsection, all it does - detects a proper RW image to run and starts it up. To provide for reliable firmware updates, the CR50 image needs to include two RW sections, while the code is running from one RW subsection, the other one can be upgraded. This patch adds the ability to generate two identical RW sections, mapped half flash size apart, and include them into the resulting EC image. To keep things simple the previously existing RW section's name is not being changed, while the new (identical) RW section is named RW_B. Two configuration options need to be defined to enable building of the new image type: CONFIG_RW_B to enable the feature and CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the flash. A new rule added to Makefile.rules allows to generate a different lds file from the same source (core/cortex-m/ec.lds.S) by defining a compile time variable to pick a different base address for the rewritable section, when RW_B is built. BRANCH=none BUG=chromium:43025 TEST=as follows: - make buildall -j still succeeds - verified that regular CR50 image starts successfully - modified chip/g/loader/main.c to launch RW_B first, re-built and re-run the image, observed on the console: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv cr50 bootloader, 20151118_11218@80881, no USB, full crypto Valid image found at 0x00084000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com] [0.001148 Inits done] This FPGA image has no USB support Console is enabled; type HELP for help. > [0.002212 task 2 waiting for events...] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (note that the image base address is 0x840000, which is RW_B). Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444 Signed-off-by: Vadim Bendebury Reviewed-on: https://chromium-review.googlesource.com/316703 Commit-Ready: Nicolas Boichat Reviewed-by: Aseda Aboagye Reviewed-by: Randall Spangler --- core/cortex-m/ec.lds.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'core') diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index d32145d243..edd5308e93 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -5,7 +5,11 @@ #include "config.h" #include "rsa.h" +#ifdef RW_B_LDS +#define FW_MEM_OFF_(section) CONFIG_##section##_B_MEM_OFF +#else #define FW_MEM_OFF_(section) CONFIG_##section##_MEM_OFF +#endif #define FW_MEM_OFF(section) (FW_MEM_OFF_(section)) #define FW_OFF(section) (CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(section)) -- cgit v1.2.1