From c6928bce0b896d6c34f386e72a859060cc59ac93 Mon Sep 17 00:00:00 2001 From: Dino Li Date: Thu, 5 Jan 2017 11:07:33 +0800 Subject: nds32: lds: reduce gap of flash - Before the change was made, the "__ro_end" was at 00013520h. We change to 00012760h. - Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE" this is because we don't support reconfiguration at board-level. - Put some task functions into "__ram_code" section to fill the gap and improving performance of code-fetch. Signed-off-by: Dino Li BRANCH=none BUG=none TEST=console commands: flasherase, flashwrite, and flashread. Change-Id: I2f2906a2a0b6971aadd00120c282801161447808 Reviewed-on: https://chromium-review.googlesource.com/424248 Commit-Ready: Dino Li Tested-by: Dino Li Reviewed-by: Randall Spangler --- core/nds32/ec.lds.S | 22 +++++++++++++++------- core/nds32/task.c | 32 ++++++++++++++++---------------- 2 files changed, 31 insertions(+), 23 deletions(-) (limited to 'core') diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 43b905c899..5955c24df1 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -28,6 +28,12 @@ MEMORY SECTIONS { .text : { + /* We put "__flash_dma_start" at the beginning of the text section + * to avoid gap. + */ + __flash_dma_start = .; + ASSERT((__flash_dma_start == 0), + "__flash_dma_start has to be 4k-byte aligned"); KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vecttable)) . = ALIGN(4); __version_struct_offset = .; @@ -35,17 +41,14 @@ SECTIONS . = ALIGN(4); KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text.vectirq)) KEEP(STRINGIFY(OUTDIR/core/CORE/init.o) (.text)) - *(.text*) - - . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); - __flash_dma_start = .; KEEP(*(.flash_direct_map)) . = ALIGN(16); KEEP(*(.ram_code)) __flash_dma_size = . - __flash_dma_start; - ASSERT((__flash_dma_size < CONFIG_IT83XX_ILM_BLOCK_SIZE), - "__flash_dma_size < CONFIG_IT83XX_ILM_BLOCK_SIZE"); - . = ALIGN(CONFIG_IT83XX_ILM_BLOCK_SIZE); + ASSERT((__flash_dma_size < IT83XX_ILM_BLOCK_SIZE), + "__flash_dma_size < IT83XX_ILM_BLOCK_SIZE"); + . = ALIGN(IT83XX_ILM_BLOCK_SIZE); + *(.text*) } > FLASH . = ALIGN(4); .rodata : { @@ -68,6 +71,11 @@ SECTIONS KEEP(*(.rodata.hcmds)) __hcmds_end = .; + . = ALIGN(4); + __mkbp_evt_srcs = .; + KEEP(*(.rodata.evtsrcs)) + __mkbp_evt_srcs_end = .; + . = ALIGN(4); __hooks_init = .; KEEP(*(.rodata.HOOK_INIT)) diff --git a/core/nds32/task.c b/core/nds32/task.c index 36f7849f2b..88bd731051 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -200,7 +200,7 @@ static inline task_ *__task_id_to_ptr(task_id_t id) * | EXT_IERx | | INT_MASK| * ------------ ----------- */ -void interrupt_disable(void) +void __ram_code interrupt_disable(void) { /* Mask all interrupts, only keep division by zero exception */ uint32_t val = (1 << 30); @@ -208,7 +208,7 @@ void interrupt_disable(void) asm volatile ("dsb"); } -void interrupt_enable(void) +void __ram_code interrupt_enable(void) { /* Enable HW2 ~ HW15 and division by zero exception interrupts */ uint32_t val = ((1 << 30) | 0xFFFC); @@ -254,7 +254,7 @@ int get_sw_int(void) * * Also includes emulation of software triggering interrupt vector */ -void syscall_handler(int desched, task_id_t resched, int swirq) +void __ram_code syscall_handler(int desched, task_id_t resched, int swirq) { /* are we emulating an interrupt ? */ if (swirq) { @@ -337,13 +337,13 @@ void update_exc_start_time(void) static volatile int ec_int; #ifdef CHIP_FAMILY_IT83XX -int intc_get_ec_int(void) +int __ram_code intc_get_ec_int(void) { return ec_int; } #endif -void start_irq_handler(void) +void __ram_code start_irq_handler(void) { /* save r0, r1, and r2 for syscall */ asm volatile ("smw.adm $r0, [$sp], $r2, 0"); @@ -442,7 +442,7 @@ static uint32_t __wait_evt(int timeout_us, task_id_t resched) return evt; } -uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait) +uint32_t __ram_code task_set_event(task_id_t tskid, uint32_t event, int wait) { task_ *receiver = __task_id_to_ptr(tskid); ASSERT(receiver); @@ -465,12 +465,12 @@ uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait) return 0; } -uint32_t task_wait_event(int timeout_us) +uint32_t __ram_code task_wait_event(int timeout_us) { return __wait_evt(timeout_us, TASK_ID_IDLE); } -uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us) +uint32_t __ram_code task_wait_event_mask(uint32_t event_mask, int timeout_us) { uint64_t deadline = get_time().val + timeout_us; uint32_t events = 0; @@ -498,14 +498,14 @@ uint32_t task_wait_event_mask(uint32_t event_mask, int timeout_us) return events & event_mask; } -uint32_t get_int_mask(void) +uint32_t __ram_code get_int_mask(void) { uint32_t ret; asm volatile ("mfsr %0, $INT_MASK" : "=r"(ret)); return ret; } -void set_int_mask(uint32_t val) +void __ram_code set_int_mask(uint32_t val) { asm volatile ("mtsr %0, $INT_MASK" : : "r"(val)); } @@ -536,7 +536,7 @@ void task_enable_all_tasks(void) __schedule(0, 0, 0); } -void task_enable_irq(int irq) +void __ram_code task_enable_irq(int irq) { uint32_t int_mask = get_int_mask(); @@ -545,7 +545,7 @@ void task_enable_irq(int irq) set_int_mask(int_mask); } -void task_disable_irq(int irq) +void __ram_code task_disable_irq(int irq) { uint32_t int_mask = get_int_mask(); @@ -554,12 +554,12 @@ void task_disable_irq(int irq) set_int_mask(int_mask); } -void task_clear_pending_irq(int irq) +void __ram_code task_clear_pending_irq(int irq) { chip_clear_pending_irq(irq); } -void task_trigger_irq(int irq) +void __ram_code task_trigger_irq(int irq) { int cpu_int = chip_trigger_irq(irq); @@ -605,7 +605,7 @@ static void ivic_init_irqs(void) set_int_priority(all_priorities); } -void mutex_lock(struct mutex *mtx) +void __ram_code mutex_lock(struct mutex *mtx) { uint32_t id = 1 << task_get_current(); @@ -632,7 +632,7 @@ void mutex_lock(struct mutex *mtx) } } -void mutex_unlock(struct mutex *mtx) +void __ram_code mutex_unlock(struct mutex *mtx) { uint32_t waiters; task_ *tsk = current_task; -- cgit v1.2.1