From 88a970c061112392f351f36584e29d27bfb1551c Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 14:52:39 -0600 Subject: driver/ppc/nx20p348x.c: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: Ie9034d5db29cb7b803f0b616a92f36aada72fee4 Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730047 Reviewed-by: Jeremy Bettis --- driver/ppc/nx20p348x.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) (limited to 'driver/ppc/nx20p348x.c') diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index e05d7e60a7..d1d315a027 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -19,8 +19,8 @@ #include "usbc_ppc.h" #include "util.h" -#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) -#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) +#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ##args) +#define CPRINTS(format, args...) cprints(CC_USBPD, format, ##args) static atomic_t irq_pending; /* Bitmask of ports signaling an interrupt. */ @@ -37,17 +37,13 @@ static uint8_t flags[CONFIG_USB_PD_PORT_MAX_COUNT]; static int read_reg(uint8_t port, int reg, int *regval) { return i2c_read8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int write_reg(uint8_t port, int reg, int regval) { return i2c_write8(ppc_chips[port].i2c_port, - ppc_chips[port].i2c_addr_flags, - reg, - regval); + ppc_chips[port].i2c_addr_flags, reg, regval); } static int nx20p348x_set_ovp_limit(int port) @@ -76,7 +72,7 @@ static int nx20p348x_is_sourcing_vbus(int port) } static int nx20p348x_set_vbus_source_current_limit(int port, - enum tcpc_rp_value rp) + enum tcpc_rp_value rp) { int regval; int status; @@ -103,7 +99,6 @@ static int nx20p348x_set_vbus_source_current_limit(int port, break; }; - return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval); } @@ -166,7 +161,8 @@ __maybe_unused static int nx20p3481_vbus_sink_enable(int port, int enable) return rv; return (status & NX20P348X_SWITCH_STATUS_HVSNK) == control ? - EC_SUCCESS : EC_ERROR_UNKNOWN; + EC_SUCCESS : + EC_ERROR_UNKNOWN; } __maybe_unused static int nx20p3481_vbus_source_enable(int port, int enable) @@ -242,7 +238,7 @@ __maybe_unused static int nx20p3483_vbus_sink_enable(int port, int enable) return rv; is_sink = (ds & NX20P3483_DEVICE_MODE_MASK) == - NX20P3483_MODE_HV_SNK; + NX20P3483_MODE_HV_SNK; if (enable == is_sink) return EC_SUCCESS; @@ -409,7 +405,7 @@ static void nx20p348x_handle_interrupt(int port) NX20P348X_DB_EXIT_FAIL_THRESHOLD) { ppc_prints("failed to exit DB mode", port); if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG, - &mask_reg)) { + &mask_reg)) { mask_reg |= NX20P348X_INT1_DBEXIT_ERR; write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask_reg); @@ -502,8 +498,8 @@ static int nx20p348x_dump(int port) int rv; ccprintf("Port %d NX20P348X registers\n", port); - for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <= - NX20P348X_DEVICE_CONTROL_REG; reg_addr++) { + for (reg_addr = NX20P348X_DEVICE_ID_REG; + reg_addr <= NX20P348X_DEVICE_CONTROL_REG; reg_addr++) { rv = read_reg(port, reg_addr, ®); if (rv) { ccprintf("nx20p: Failed to read register 0x%x\n", -- cgit v1.2.1 From c86ea22ff6ea09dd1dd1778f4e1c0f924473d95a Mon Sep 17 00:00:00 2001 From: "amber.chen" Date: Thu, 21 Jul 2022 18:18:43 +0800 Subject: NX20P348x: enable RCP 5V SRC mask function enable RCP 5V SRC mask function BRANCH=none BUG=b:237468526 TEST=make -j BOARD=taniks Signed-off-by: amber.chen Change-Id: I47c7ad99c0ab2141d8e08f5ac385250353ed8227 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3779857 Reviewed-by: Boris Mittelberg --- driver/ppc/nx20p348x.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'driver/ppc/nx20p348x.c') diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index d1d315a027..88903d3587 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -315,6 +315,10 @@ static int nx20p348x_init(int port) /* Unmask Fast Role Swap detect interrupt */ mask &= ~NX20P3481_INT1_FRS_DET; } + if (IS_ENABLED(CONFIG_USBC_NX20P348X_RCP_5VSRC_MASK_ENABLE)) { + /* Mask RCP 5V SRC */ + mask |= NX20P348X_INT1_RCP_5VSRC; + } rv = write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask); if (rv) return rv; -- cgit v1.2.1 From 71b2ef709dcb14260f5fdaa3ab4ced005a29fb46 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 12 Sep 2022 14:54:36 -0400 Subject: Update license boilerplate text in source code files Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis Reviewed-by: Jack Rosenthal --- driver/ppc/nx20p348x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'driver/ppc/nx20p348x.c') diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c index 88903d3587..d202898a85 100644 --- a/driver/ppc/nx20p348x.c +++ b/driver/ppc/nx20p348x.c @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -- cgit v1.2.1