From 65135e2c0482c5d6c80bf0049136a88a0a4301f3 Mon Sep 17 00:00:00 2001 From: Jack Rosenthal Date: Mon, 27 Jun 2022 15:05:51 -0600 Subject: driver/usb_mux/ps8822.h: Format with clang-format BUG=b:236386294 BRANCH=none TEST=none Change-Id: I24ae2b1082c89719fdd2b373a4a152292cf4d67f Signed-off-by: Jack Rosenthal Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730170 Reviewed-by: Jeremy Bettis --- driver/usb_mux/ps8822.h | 64 ++++++++++++++++++++++++------------------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'driver/usb_mux/ps8822.h') diff --git a/driver/usb_mux/ps8822.h b/driver/usb_mux/ps8822.h index 86b911db70..282a30e642 100644 --- a/driver/usb_mux/ps8822.h +++ b/driver/usb_mux/ps8822.h @@ -11,48 +11,48 @@ #include "usb_mux.h" -#define PS8822_I2C_ADDR0_FLAG 0x10 -#define PS8822_I2C_ADDR1_FLAG 0x18 -#define PS8822_I2C_ADDR2_FLAG 0x58 -#define PS8822_I2C_ADDR3_FLAG 0x60 +#define PS8822_I2C_ADDR0_FLAG 0x10 +#define PS8822_I2C_ADDR1_FLAG 0x18 +#define PS8822_I2C_ADDR2_FLAG 0x58 +#define PS8822_I2C_ADDR3_FLAG 0x60 -#define PS8822_REG_PAGE0 0x00 +#define PS8822_REG_PAGE0 0x00 /* Mode register for setting mux */ -#define PS8822_REG_MODE 0x01 -#define PS8822_MODE_ALT_DP_EN BIT(7) -#define PS8822_MODE_USB_EN BIT(6) -#define PS8822_MODE_FLIP BIT(5) -#define PS8822_MODE_PIN_E BIT(4) +#define PS8822_REG_MODE 0x01 +#define PS8822_MODE_ALT_DP_EN BIT(7) +#define PS8822_MODE_USB_EN BIT(6) +#define PS8822_MODE_FLIP BIT(5) +#define PS8822_MODE_PIN_E BIT(4) -#define PS8822_REG_CONFIG 0x02 +#define PS8822_REG_CONFIG 0x02 #define PS8822_CONFIG_HPD_IN_DIS BIT(7) -#define PS8822_CONFIG_DP_PLUG BIT(6) +#define PS8822_CONFIG_DP_PLUG BIT(6) -#define PS8822_REG_DEV_ID1 0x06 -#define PS8822_REG_DEV_ID2 0x07 -#define PS8822_REG_DEV_ID3 0x08 -#define PS8822_REG_DEV_ID4 0x09 -#define PS8822_REG_DEV_ID5 0x0A -#define PS8822_REG_DEV_ID6 0x0B +#define PS8822_REG_DEV_ID1 0x06 +#define PS8822_REG_DEV_ID2 0x07 +#define PS8822_REG_DEV_ID3 0x08 +#define PS8822_REG_DEV_ID4 0x09 +#define PS8822_REG_DEV_ID5 0x0A +#define PS8822_REG_DEV_ID6 0x0B #define PS8822_ID_LEN 6 -#define PS8822_REG_PAGE1 0x01 -#define PS8822_REG_DP_EQ 0xB6 -#define PS8822_DP_EQ_AUTO_EN BIT(7) +#define PS8822_REG_PAGE1 0x01 +#define PS8822_REG_DP_EQ 0xB6 +#define PS8822_DP_EQ_AUTO_EN BIT(7) -#define PS8822_DPEQ_LEVEL_UP_9DB 0x00 -#define PS8822_DPEQ_LEVEL_UP_11DB 0x01 -#define PS8822_DPEQ_LEVEL_UP_12DB 0x02 -#define PS8822_DPEQ_LEVEL_UP_14DB 0x03 -#define PS8822_DPEQ_LEVEL_UP_17DB 0x04 -#define PS8822_DPEQ_LEVEL_UP_18DB 0x05 -#define PS8822_DPEQ_LEVEL_UP_19DB 0x06 -#define PS8822_DPEQ_LEVEL_UP_20DB 0x07 -#define PS8822_DPEQ_LEVEL_UP_21DB 0x08 -#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F -#define PS8822_REG_DP_EQ_SHIFT 3 +#define PS8822_DPEQ_LEVEL_UP_9DB 0x00 +#define PS8822_DPEQ_LEVEL_UP_11DB 0x01 +#define PS8822_DPEQ_LEVEL_UP_12DB 0x02 +#define PS8822_DPEQ_LEVEL_UP_14DB 0x03 +#define PS8822_DPEQ_LEVEL_UP_17DB 0x04 +#define PS8822_DPEQ_LEVEL_UP_18DB 0x05 +#define PS8822_DPEQ_LEVEL_UP_19DB 0x06 +#define PS8822_DPEQ_LEVEL_UP_20DB 0x07 +#define PS8822_DPEQ_LEVEL_UP_21DB 0x08 +#define PS8822_DPEQ_LEVEL_UP_MASK 0x0F +#define PS8822_REG_DP_EQ_SHIFT 3 /** * Set DP Rx Equalization value -- cgit v1.2.1