From e616b66c76ddbdf03ed8d2179516c9c67cfc045a Mon Sep 17 00:00:00 2001 From: Peter Marheine Date: Mon, 4 Jul 2022 12:33:49 +1000 Subject: it8xxx2: disable eSPI inputs when in G3 eSPI CS# goes low when the AP is off, which prevents the EC from entering deep doze to save power. Disable the eSPI pad on G3 entry and re-enable before exiting G3 to enable EC power saving. This optimization is expected to be relevant to all boards that use eSPI to manage AP power with IT8xxx2, so the code is located such that it will be included for every board that has appropriate configuration. BUG=b:237717730 TEST=Nereid still boots from G3 and returns to G3 correctly; debug logs indicate eSPI pad control is running. BRANCH=none Signed-off-by: Peter Marheine Change-Id: Ia2f245b0fc84cdddf28471a13a69e73b6188f932 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3742840 Reviewed-by: Andrew McRae Reviewed-by: Keith Short --- zephyr/app/ec/chip/CMakeLists.txt | 1 + zephyr/app/ec/chip/riscv/CMakeLists.txt | 1 + zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt | 3 ++ zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c | 63 +++++++++++++++++++++++ 4 files changed, 68 insertions(+) create mode 100644 zephyr/app/ec/chip/CMakeLists.txt create mode 100644 zephyr/app/ec/chip/riscv/CMakeLists.txt create mode 100644 zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt create mode 100644 zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c (limited to 'zephyr/app/ec/chip') diff --git a/zephyr/app/ec/chip/CMakeLists.txt b/zephyr/app/ec/chip/CMakeLists.txt new file mode 100644 index 0000000000..e92dbc5d5d --- /dev/null +++ b/zephyr/app/ec/chip/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory_ifdef(CONFIG_RISCV riscv) \ No newline at end of file diff --git a/zephyr/app/ec/chip/riscv/CMakeLists.txt b/zephyr/app/ec/chip/riscv/CMakeLists.txt new file mode 100644 index 0000000000..b11c4e9a90 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory_ifdef(CONFIG_SOC_FAMILY_RISCV_ITE riscv-ite) \ No newline at end of file diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt new file mode 100644 index 0000000000..69608c33e3 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/riscv-ite/CMakeLists.txt @@ -0,0 +1,3 @@ +if (CONFIG_ESPI_IT8XXX2) + zephyr_library_sources_ifdef(CONFIG_AP_POWER_CONTROL it8xxx2-espi.c) +endif () \ No newline at end of file diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c new file mode 100644 index 0000000000..81d96c4328 --- /dev/null +++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c @@ -0,0 +1,63 @@ +/* Copyright 2022 The ChromiumOS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(ec_chip_it8xxx2_espi, CONFIG_ESPI_LOG_LEVEL); + +/* + * When eSPI CS# is held low, it prevents IT8xxx2 from entering deep doze. + * To allow deep doze and save power, disable the eSPI inputs while the AP is + * in G3. + */ +static const struct device *const espi_device = + DEVICE_DT_GET(DT_NODELABEL(espi0)); + +static void espi_enable_callback(struct ap_power_ev_callback *cb, + struct ap_power_ev_data data) +{ + switch (data.event) { + case AP_POWER_INITIALIZED: + /* When AP power state becomes known, sync eSPI enable */ + if (chipset_in_state(CHIPSET_STATE_HARD_OFF)) { + LOG_DBG("AP off; disabling eSPI"); + espi_it8xxx2_enable_pad_ctrl(espi_device, false); + } + break; + case AP_POWER_PRE_INIT: + case AP_POWER_HARD_OFF: { + bool enable = data.event == AP_POWER_PRE_INIT; + + LOG_DBG("%sabling eSPI in response to AP power event", + enable ? "en" : "dis"); + espi_it8xxx2_enable_pad_ctrl(espi_device, enable); + break; + } + default: + __ASSERT(false, "%s: unhandled event: %d", __func__, + data.event); + break; + } +} + +static int init_espi_enable_callback(const struct device *unused) +{ + static struct ap_power_ev_callback cb; + + if (!device_is_ready(espi_device)) + k_oops(); + + ap_power_ev_init_callback(&cb, espi_enable_callback, + AP_POWER_INITIALIZED | AP_POWER_PRE_INIT | + AP_POWER_HARD_OFF); + ap_power_ev_add_callback(&cb); + + return 0; +} +/* Should run before power sequencing init so INITIALIZED callback can fire */ +SYS_INIT(init_espi_enable_callback, APPLICATION, 0); -- cgit v1.2.1 From 5d0edcf6d2db6a8d7701c8bcfc59c5bb58326e5f Mon Sep 17 00:00:00 2001 From: Keith Short Date: Thu, 21 Jul 2022 13:32:06 -0600 Subject: zephyr: Delete CONFIG_PLATFORM_EC_MPU CONFIG_PLATFORM_EC_MPU is redundant with the Zephyr Kconfig option, CONFIG_MPU. Use the Zephyr option directly. BUG=none BRANCH=none TEST=zmake testall --static; compare binaries Signed-off-by: Keith Short Change-Id: Iff92c7e9fe3a003366d153e618d2450b367fd169 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3791660 Reviewed-by: Aaron Massey --- zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec | 4 ++++ zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'zephyr/app/ec/chip') diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec index d05ad020e7..6a78792733 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec @@ -8,6 +8,10 @@ if SOC_FAMILY_MEC +# Enable MPU for ARM targets +config ARM_MPU + default y + # ADC config PLATFORM_EC_ADC_RESOLUTION default 10 diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx index 2da9252775..2e3d3c95a0 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx @@ -8,6 +8,10 @@ if SOC_FAMILY_NPCX +# Enable MPU for ARM targets +config ARM_MPU + default y + # Enable NPCX firmware header generator config NPCX_HEADER default y -- cgit v1.2.1 From 0096058366ada3cfbaf8aa3c1ffcca99d984f263 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 4 Aug 2022 07:57:41 +0000 Subject: zephyr: shim: add all missing include/ prefixes Add all the missing include/ prefixes to the various #include around the zephyr tests so that they build with LEGACY_INCLUDE_PATH=n. BRANCH=none BUG=none TEST=zmake testall Cq-Depend: chromium:3807663 Change-Id: I81cea4f291eea61e674ef2fa61bdc60407c5f142 Signed-off-by: Fabio Baltieri Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3810411 Reviewed-by: Keith Short --- zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'zephyr/app/ec/chip') diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c index 81d96c4328..88fd96c9d2 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c +++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c @@ -5,8 +5,8 @@ #include #include #include -#include -#include +#include +#include LOG_MODULE_REGISTER(ec_chip_it8xxx2_espi, CONFIG_ESPI_LOG_LEVEL); -- cgit v1.2.1 From 71b2ef709dcb14260f5fdaa3ab4ced005a29fb46 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 12 Sep 2022 14:54:36 -0400 Subject: Update license boilerplate text in source code files Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis Reviewed-by: Jack Rosenthal --- zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec | 2 +- zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x | 2 +- zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx | 2 +- zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 | 2 +- zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 | 2 +- zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 | 2 +- zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'zephyr/app/ec/chip') diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec index 6a78792733..3baca08d04 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x index 9e37b6a534..bfcfeb8235 100644 --- a/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x +++ b/zephyr/app/ec/chip/arm/microchip_xec/Kconfig.xec_mec172x @@ -1,4 +1,4 @@ -# Copyright 2022 The Chromium OS Authors. All rights reserved. +# Copyright 2022 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx index 2e3d3c95a0..17936ab05d 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 index 37561f4dad..cb00db3345 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx7 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 index aceec4f3ca..9c807a732c 100644 --- a/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 +++ b/zephyr/app/ec/chip/arm/nuvoton_npcx/Kconfig.npcx9 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 index 809b9a6401..e0ea15c5b7 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 +++ b/zephyr/app/ec/chip/riscv/riscv-ite/Kconfig.it8xxx2 @@ -1,4 +1,4 @@ -# Copyright 2021 The Chromium OS Authors. All rights reserved. +# Copyright 2021 The ChromiumOS Authors # Use of this source code is governed by a BSD-style license that can be # found in the LICENSE file. diff --git a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c index 88fd96c9d2..6109964cb9 100644 --- a/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c +++ b/zephyr/app/ec/chip/riscv/riscv-ite/it8xxx2-espi.c @@ -1,4 +1,4 @@ -/* Copyright 2022 The ChromiumOS Authors. +/* Copyright 2022 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ -- cgit v1.2.1