From 32a3d94e879efebef135062342fdbd9dae8ec463 Mon Sep 17 00:00:00 2001 From: Diana Z Date: Fri, 12 May 2023 10:25:48 -0600 Subject: AMD Mux Emul: Stabilize delayed mux set code The current emulator relies on timing in order to delay mux sets. However, this can lead to some surprising mismatches in time between the emulator and test (such as the write completing during a subsequent test case). Instead, delay by the number of reads the driver has done. BUG=b:234771735 TEST=./twister -s drivers/drivers.amd_fp6_usb_mux Change-Id: I71c78348e29b70c479da8009b8a085cf4e57c188 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4528795 Reviewed-by: Jeremy Bettis Commit-Queue: Diana Z Tested-by: Diana Z --- zephyr/emul/emul_amd_fp6.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'zephyr/emul/emul_amd_fp6.c') diff --git a/zephyr/emul/emul_amd_fp6.c b/zephyr/emul/emul_amd_fp6.c index dfb763e1c8..b0b618fd6a 100644 --- a/zephyr/emul/emul_amd_fp6.c +++ b/zephyr/emul/emul_amd_fp6.c @@ -28,8 +28,8 @@ enum amd_fp6_read_bytes { struct amd_fp6_data { struct i2c_common_emul_data common; - int64_t finish_delay; /* How long before mux set "completes"? */ - int64_t set_time; /* Time of last set call */ + int finish_delay; /* How many reads before mux set "completes"? */ + int waiting_reads; /* How many reads have we waited to complete? */ uint8_t last_mux_set; /* Last value of mux set call */ uint8_t regs[AMD_FP6_MAX_REG]; }; @@ -58,11 +58,11 @@ void amd_fp6_emul_reset_regs(const struct emul *emul) data->regs[AMD_FP6_PORT1] = 0; } -void amd_fp6_emul_set_delay(const struct emul *emul, int delay_ms) +void amd_fp6_emul_set_delay(const struct emul *emul, int delay_reads) { struct amd_fp6_data *data = (struct amd_fp6_data *)emul->data; - data->finish_delay = delay_ms; + data->finish_delay = delay_reads; } void amd_fp6_emul_set_xbar(const struct emul *emul, bool ready) @@ -87,11 +87,11 @@ static int amd_fp6_emul_read(const struct emul *emul, int reg, uint8_t *val, /* Decide if we've finally finished our operation */ if (pos == AMD_FP6_PORT0 && data->finish_delay > 0) { - int64_t uptime = k_uptime_delta(&data->set_time); + data->waiting_reads++; if (((regs[pos] >> AMD_FP6_MUX_PORT_STATUS_OFFSET) == AMD_FP6_MUX_PORT_CMD_BUSY) && - (uptime >= data->finish_delay)) + (data->waiting_reads >= data->finish_delay)) regs[pos] = amd_fp6_emul_mux_complete(data->last_mux_set); } @@ -113,11 +113,13 @@ static int amd_fp6_emul_write(const struct emul *emul, int reg, uint8_t val, data->last_mux_set = val; - if (data->finish_delay == 0) + if (data->finish_delay == 0) { regs[AMD_FP6_PORT0] = amd_fp6_emul_mux_complete(val); - else + } else { + data->waiting_reads = 0; regs[AMD_FP6_PORT0] = AMD_FP6_MUX_PORT_CMD_BUSY << AMD_FP6_MUX_PORT_STATUS_OFFSET; + } return 0; } -- cgit v1.2.1